Deep convolutional network heterogeneous architecture

A mobile computing device comprising:

• an imaging sensor that captures images;
• a system on chip (SoC) that implements a deep convolutional neural network architecture, the SoC, including:
• an SoC bus;
• an on-chip memory coupled to the SoC bus;
• a configurable accelerator framework coupled to the SoC bus, the configurable accelerator framework including a reconfigurable dataflow accelerator fabric that receives the captured images from the imaging sensor for deep convolutional neural network (DCNN) processing by at least one convolution accelerator;
• and
• a plurality of digital signal processor (DSPs) clusters coupled to the SoC bus, the plurality of DSP clusters configured to perform non-convolution operations for the DCNN and arranged to coordinate functionality with the at least one convolution accelerator of the configurable accelerator framework to execute the DCNN, wherein the plurality of DSP clusters are configured to perform the non-convolutional data processing operations for a DCNN kernel in parallel with execution of convolutional operations for the DCNN kernel by the at least one convolutional accelerator, wherein the non-convolutional data processing operations for the DCNN kernel include one or more operations selected from a group of operations consisting of pooling, non-linear activation and cross-channel response normalization.

A system on a chip (SoC), comprising:

• a communication bus;
• a memory coupled to the communication bus;
• a configurable accelerator framework coupled to the communication bus, the configurable accelerator framework having a reconfigurable stream switch coupled to the communication bus and a plurality of convolution accelerators coupled to the stream switch, the plurality of convolution accelerators arranged to perform convolution operations on image data during execution of a deep convolutional neural network (DCNN);
• and
• a plurality of digital signal processors (DSPs) coupled to the communication bus, wherein the plurality of DSPs perform non-convolution operations for the DCNN and coordinate functionality with the plurality of convolution accelerators of the configurable accelerator framework to execute the DCNN, wherein the plurality of DSP are configured to perform non-convolutional data processing operations for a DCNN kernel in parallel with execution of convolutional operations for the DCNN kernel by the plurality of convolutional accelerators, wherein the non-convolutional data processing operations for the DCNN kernel include one or more operations selected from a group of operations consisting of pooling, non-linear activation and cross-channel response normalization.