Distributed scheduler providing execution pipe balance

A processor, comprising:

• a plurality of execution pipes;
• and
• a multimodal distributed scheduler coupled to the plurality of execution pipes and comprising:
• a first queue configured to buffer instruction operations from a front end of an instruction pipeline of the processor;
• a plurality of second queues, each second queue configured to buffer instruction operations allocated from the first queue for a corresponding separate subset of execution pipes of the plurality of execution pipes;
• and
• a queue controller configured to:
• select an allocation mode from a plurality of allocation modes based on whether at least one indicator of an imbalance at the multimodal distributed scheduler is detected, wherein each allocation mode of the plurality of allocation modes corresponds to a respective configuration for at least a portion of the multimodal distributed scheduler;
• and
• configure the multimodal distributed scheduler to allocate instruction operations from the first queue among the plurality of second queues in accordance with the selected allocation mode.

A processor, comprising:

• a plurality of execution pipes;
• and
• a multimodal distributed scheduler coupled to the plurality of execution pipes and comprising:
• a first queue configured to buffer instruction operations from a front end of an instruction pipeline of the processor;
• a plurality of second queues, each second queue configured to buffer instruction operations allocated from the first queue for a corresponding separate subset of execution pipes of the plurality of execution pipes;
• and
• a queue controller configured to:
• configure at least a portion of the multimodal distributed scheduler, for each instruction operation of a subset of instruction operations in the first queue, to:
• speculatively allocate a copy of the instruction operation from the first queue to each second queue;
• and
• invalidate the copies of the instruction operation in all but one second queue based on current pipe occupancies of execution pipes capable of executing the instruction operation.

A processor, comprising:

• a plurality of execution pipes;
• and
• a distributed multimodal scheduler coupled to the plurality of execution pipes and comprising:
• a first queue configured to buffer instruction operations from a front end of an instruction pipeline of the processor;
• a plurality of second queues, each second queue configured to buffer instruction operations allocated from the first queue for a corresponding separate subset of execution pipes of the plurality of execution pipes;
• and
• a queue controller configured to configure at least a portion of the multimodal distributed scheduler to:
• allocate sets of instruction operations from the first queue among the plurality of second queues in an interleaving pattern;
• and
• for each set, select a second queue to which an initial instruction operation of the set is to be allocated in the interleaving pattern based on one of:
• a predefined sequence or pseudo-randomly.