Branch target buffer miss handling

A method, comprising:

• in a microprocessor comprising:
• an instruction cache;
• an instruction fetch unit (IFU);
• and
• a prediction unit (PRU) comprising a branch target buffer (BTB);
• wherein each entry of the BTB is associated with a fetch block (FBlk),
• wherein each entry comprises:
• a length of the FBlk;
• and
• a termination type of the FBIk;
• wherein a FBlk comprises a sequential set of instructions starting at a fetch address (FA), wherein the length of the FBlk is no longer than a predetermined maximum length, and wherein the termination type of the FBlk is from a list comprising:
• a sequential termination type indicating that a FA of a next FBlk in program order after the FBlk is sequential to a last instruction of the FBIk;
• and
• one or more non-sequential termination types;
• using the FA of a current FBlk to generate a current BTB lookup value;
• looking up the current BTB lookup value in the BTB;
• and
• in response to a miss of the current BTB lookup value in the BTB, predicting that the current FBlk has:
• a length that is the predetermined maximum length;
• and
• a termination type that is sequential;
• using, by the IFU, the FA of the current FBlk and the predicted predetermined maximum length of the current FBIk to fetch the current FBlk from the instruction cache;
• and
• in response to a miss of a BTB lookup value in the BTB:
• incrementing, by the PRU, a counter that indicates a number of outstanding BTB misses;
• and
• pausing, by the PRU, the IFU from fetching FBlks from the instruction cache by pausing making predictions if the counter indicates the number of outstanding BTB misses is greater than a predetermined number.

A non-transitory computer-readable medium having instructions stored thereon that are capable of causing or configuring a microprocessor comprising:

• a prediction unit (PRU) comprising a branch target buffer (BTB);
• wherein each entry of the BTB is associated with a fetch block (FBlk), wherein each entry comprises:
• a length of the FBIk;
• and
• a termination type of the FBIk;
• wherein a FBlk comprises a sequential set of instructions starting at a fetch address (FA), wherein the length of the FBlk is no longer than a predetermined maximum length, and wherein the termination type of the FBlk is from a list comprising:
• a sequential termination type indicating that a FA of a next FBlk in program order after the FBlk is sequential to a last instruction of the FBlk;
• and
• one or more non-sequential termination types;
• wherein the PRU is configured to:
• use the FA of a current FBlk to generate a current BTB lookup value;
• look up the current BTB lookup value in the BTB;
• and
• in response to a miss of the current BTB lookup value in the BTB, predict that the current FBlk has:
• a length that is the predetermined maximum length;
• and
• a termination type that is sequential;
• and
• an instruction fetch unit (IFU) configured to use the FA of the current FBlk and the predicted predetermined maximum length of the current FBlk to fetch the current FBlk from an instruction cache of the microprocessor;
• and
• a counter that indicates a number of outstanding BTB misses;
• wherein the PRU is further configured to, in response to a miss of a BTB lookup value in the BTB:
• increment the counter;
• and
• pause the IFU from fetching FBlks from the instruction cache by pausing making predictions if the counter indicates the number of outstanding BTB misses is greater than a predetermined number.