Cache coherence validation using delayed fulfillment of L2 requests

A computing system comprising:

• a first processing element;
• a second processing element;
• an interconnect connected to the first processing element and the second processing element;
• the first processing element being configured to:
• detect a load instruction requesting a processing element to transfer data from a target cache line in a global memory location to a local memory location, the global memory location being accessible by the first processing element and the second processing element, and the local memory location being accessible by the first processing element;
• apply, in response to detecting the load instruction requesting the first processing element to transfer the data from the target cache line in the global memory location to the local memory location, a delay in the global memory location to delay the transfer of the data from the target cache line in the global memory location to the local memory location, wherein application of the delay to the transfer of the data increases a window of opportunity for the second processing element to make changes to the target cache line in the global memory location to create an out-of-order hazard and wherein the delay is based on a distance between the first processing element and other processing elements in the computing system;
• execute the load instruction and transfer the data from the target cache line in the global memory location to the local memory location with the applied delay;
• and
• validate, in response to the execution of the load instruction and transferring the data with the applied delay, a cache coherence of the computing system.

A processing element comprising:

• a processor pipeline comprising one or more load store units (LSUs) configured to execute load and store instructions, the one or more LSUs being configured to:
• detect a load instruction requesting the processing element to transfer data from target cache line in a global memory location to a local memory location, the processing element being among a plurality of processing elements of a data processing system;
• apply, in response to detecting the load instruction requesting the processing element to transfer the data from the target cache line in the global memory location to the local memory location, a delay in the global memory location to delay the transfer of the data from the target cache line in the global memory location to the local memory location, wherein application of the delay to the transfer of the data increases a window of opportunity for the another processing element to make changes to the target cache line in the global memory location to create an out-of-order hazard, and wherein the delay is based on a distance between the processing element and other processing elements in the data processing system;
• execute the load instruction and transfer the data from the target cache line in the global memory location to the local memory location with the applied delay;
• and
• validate, in response to executing the load instruction and transferring the data with the applied delay, a cache coherence of the data processing system including the processing element.