US 12,118,333 B2Granted

Semiconductor device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsTakayuki Ikeda, Roh Yamamoto, Shuichi Katsui

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Abstract

A semiconductor device that updates a weight coefficient used for arithmetic operation by an artificial neural network is provided. Each of the first to third memory cells draws a current corresponding to data of its retention node and changes the data in accordance with the potentials of first and second wirings. When a weight coefficient and first and second reference data are held in the retention nodes of the first to third memory cells, the first circuit supplies, to a third wiring, a constant currents drawn by the second and third memory cells. When input data is input to the first wiring, a difference current between the constant current and a current drawn by the first memory cell is changed, and the second circuit outputs arithmetic result data corresponding to the change. The third circuit inputs update data corresponding to the arithmetic result data to the second wiring.

Claims20

Dependent claims

A semiconductor device comprising:

a first circuit configured to perform first arithmetic operation using a first data and a second data according to a predetermined formula, in order to output a first result;
a second circuit configured to output a first potential using a first current corresponding to the first result;
a third circuit configured to perform second arithmetic operation using the first result, the second data, and teacher data, and to output a second potential corresponding to a second result of the second arithmetic operation;
and
a first memory cell electrically connected to the third circuit, the first memory cell storing a third potential,
a second memory cell electrically connected to the first circuit, the second memory cell configured to store a fourth potential corresponding to the first data,
a third memory cell electrically connected to the first circuit and the third circuit, the third memory cell configured to store a fifth potential corresponding to the second data,
wherein the teacher data is data input from outside to the third circuit,
wherein the first circuit is configured to output the first current into the second circuit,
wherein the third circuit is configured to receive the first potential output from the second circuit,
wherein the first result is a result of the first arithmetic operation using the first data and the second data, and
wherein the second result is configured to be input to the third memory cell to update the second data.

9 more elements

A semiconductor device comprising:

a first circuit electrically connected to a first memory cell through a first wiring;
a second circuit electrically connected to the first circuit through the first wiring;
and
a third circuit electrically connected to the first memory cell through a second wiring,
wherein the third circuit is electrically connected to the first memory cell through a third wiring,
wherein the third circuit comprises an input terminal,
wherein the first memory cell comprises a retention node,
wherein the first memory cell is configured to change a potential of the retention node of the first memory cell in accordance with a change in a potential of the second wiring,
wherein the first memory cell is configured to change the potential of the retention node of the first memory cell in accordance with a change in a potential of the third wiring,
wherein the first memory cell is configured to make a current corresponding to the potential of the retention node of the first memory cell flow between the first memory cell and the first wiring,
wherein the first circuit is configured to supply a current to the first wiring,
wherein the second circuit is configured to generate a first potential corresponding to a first current that flows between the first wiring and the second circuit and to output the first potential to the third circuit,
wherein a second potential is input to the input terminal of the third circuit, and
wherein the third circuit is configured to change the potential of the third wiring by the first potential, the second potential, and the potential of the second wiring.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/050,359Filed 15 Apr 2019
Priority: JP 2018-08471326 Apr 2018
Published: US 2021/0318856 A114 Oct 2021
Granted: 15 Oct 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification20 codes

G06F 7/60
Methods or arrangements for processing data by operating upon the order or content of the data handled: methods or arrangements for performing…
G06F 7/57
Using non-contact-making devices, e.g. tube, solid state device; using unspecified devices: arithmetic logic units [ALU], i.e. arrangements or…
G06N 3/048
Architecture, e.g. interconnection topology: activation functions
G06N 3/0499
Architecture, e.g. interconnection topology: feedforward networks

Family

US 2021/0318856 A1Pre-grant publication · published 14 Oct 2021
US 12,118,333 B2This patent

From the US filing history. Foreign family members aren’t listed.

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