US 12,118,331 B2 · Bias unit element with binary weighted charge transfer lines

Abstract

A Bias Unit Element (UE) comprises NAND gates with complementary outputs, the complementary outputs coupled through a charge transfer capacitor to a differential charge transfer bus comprising positive charge transfer lines and negative charge transfer lines. Each line of the differential charge transfer bus has a particular binary weighted line weight, such as 1, 2, 4, 2, 4, 8, and 4, 8, 16. Digital bias inputs are provided to the Bias UE NAND gate inputs, with a clear bit to initialize charge, and a sign input for enabling one of a positive Bias UE or negative Bias UE. A low-to-high transition causes a transfer of charge to the binary weighted charge transfer bus, thereby adding or subtracting a bias value from the charge transfer bus.

Claims21

Dependent claims

A Bias Unit Element (UE) receiving an E digital input with an enable bit and generating charge coupled to a charge transfer bus comprising charge transfer lines, each charge transfer line having an associated weight, the Bias UE comprising:

a plurality of logic gates, each logic gate having an input coupled to an E digital input bit and the enable bit and generating a positive output and a negative output;
the positive output coupled through a first charge transfer capacitor to a positive charge transfer line, the negative output coupled through a second charge transfer capacitor to a negative charge transfer line;
each charge transfer line having an associated binary weight, the binary weight for each charge transfer line including at least weights 1, 2, 4, 8, and 16.

A Bias Unit Element (UE) receiving a digital bias value E, a clear bit input, and a sign bit input, the Bias UE generating a bias charge coupled to a differential charge transfer bus in response to the digital bias value E, the Bias UE comprising:

a positive Bias UE enabled when the sign bit input is positive;
a negative Bias UE enabled when the sign bit input is negative;
the positive bias UE comprising a plurality of logic gates, each logic gate coupled to one of the digital bias E bits, the sign bit input, and the clear bit input, each logic gate generating a positive output and a negative output which is the complement of the positive output, each positive output of each of the plurality of logic gates coupled through a charge transfer capacitor to a respective negative charge transfer line and each negative output of each of the plurality of logic gates coupled through a charge transfer capacitor to a respective positive charge transfer line;
the negative bias UE comprising a plurality of logic gates, each logic gate coupled to one of the digital bias E bits, the sign bit input, and the clear bit input, each logic gate generating a positive output and a negative output which is the complement of the positive output, each positive output of each of the plurality of logic gates coupled through a different charge transfer capacitor to a respective positive charge transfer line and the negative output of each of the plurality of logic gates coupled through a different charge transfer capacitor to a respective negative charge transfer line.

1 more element

Dependencies are inferred from the claim text.

Bias unit element with binary weighted charge transfer lines

Life of this patent

Bias unit element with binary weighted charge transfer lines

Life of this patent

Abstract

Claims21