Low power multiplier with non-linear polar material based reset mechanism with sequential reset

An apparatus comprising:

• an AND gate to receive a multiplier and a multiplicand;
• a 1-bit full adder comprising a majority gate or a minority gate directly connected to an output of the AND gate, wherein the 1-bit full adder comprises non-linear polar material, and wherein the 1-bit full adder is to receive a sum input and a carry input;
• and
• a reset mechanism comprising logic to condition first terminals of a set of capacitors of the 1-bit full adder, the set of capacitors comprising the non-linear polar material, wherein the reset mechanism is to reset second terminals of the set of capacitors sequentially during a reset phase separate from an evaluation phase, wherein the reset mechanism is to apply a predetermined input to the multiplier, the multiplicand, the sum input, and the carry input during the reset phase.

A system comprising:

• a processor circuitry to execute one or more instructions;
• a communication interface communicatively coupled to the processor circuitry;
• and
• a memory coupled to the processor circuitry, wherein the processor circuitry comprises a multiplier circuitry which includes:
• an AND gate comprising non-linear polar material;
• and
• a reset mechanism comprising logic to condition first terminals of a set of capacitors of the AND gate, the set of capacitors comprising non-linear polar material, wherein the reset mechanism is to reset second terminals of the set of capacitors sequentially during a reset phase separate from an evaluation phase.