Automatic generation of sub-cells for an analog integrated circuit

A system, comprising:

• a processing device;
• and
• a storage device operably connected to the processing device and storing instructions, that when executed by the processing device, cause operations to be performed, the operations comprising:
• receiving partition information for an analog integrated circuit, wherein the partition information defines types of sub-cells within the analog integrated circuit, each of the types of sub-cells having a corresponding size and functionality and wherein the corresponding size and functionality both vary between the types of sub-cells;
• determining, based on the partition information, first cut locations along a first direction and second cut locations along a second direction of a non-final layout of the integrated circuit, the first direction and the second direction being orthogonal to each other;
• partitioning the non-final layout into a plurality of sub-cells based on the first cut locations and the second cut locations;
• and
• merging the plurality of sub-cells to produce a layout diagram of the analog integrated circuit.

A method, comprising:

• receiving partition information for an analog cell, wherein the partition information defines types of sub-cells within the analog cell, each of the types of sub-cells having a corresponding size and functionality and wherein the corresponding size and functionality both vary between the types of sub-cells;
• determining, based on the partition information, first cut locations along a first direction and second cut locations along a second direction of a non-final layout of an integrated circuit, the first direction and the second direction being orthogonal to each other;
• partitioning the non-final layout into a plurality of sub-cells based on the first cut locations and the second cut locations;
• verifying each sub-cell in the plurality of sub-cells;
• and
• producing a layout of the integrated circuit using the plurality of sub-cells.