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AssigneesUniversity of Florida Research Foundation, Inc., Intel Corporation
InventorsSwarup Bhunia, Abdulrahman Alaql, Nij Dorairaj, David Kehlet
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In general, embodiments of the present disclosure provide methods, apparatus, systems, computer program products, computing devices, computing entities, and/or the like for altering a design of a hardware intellectual property (IP). In accordance with various embodiments, a representation of the design of the hardware IP is converted to generate a control and data flow graph (CDFG) for the design. An entropy analysis of the CDFG is conducted to identify one or more control paths and/or data paths for removal. Responsive to identifying control path(s) for removal, control logic for the control path(s) is removed from the design and replaced with first reconfigurable logic. Responsive to identifying data path(s) for removal, datapath logic for the data path(s) is removed from the design and replaced with second reconfigurable logic. Logic synthesis is then performed on the design, along with verification to check functional correctness of the design of the hardware.
A computer-implemented method comprising:
An apparatus comprising one or more processors and at least one memory comprising computer executable instructions, the at least one memory and the computer executable instructions configured to, with the one or more processors, cause the apparatus to:
A computer program product comprising at least one non-transitory computer-readable storage medium having computer-readable program code portions stored therein, the computer-readable program code portions comprising executable portions configured to cause one or more processors to:
Dependencies are inferred from the claim text.