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US 12,118,247 B2Granted
Performance of bank refresh
AssigneeAdvanced Micro Devices, Inc.
InventorsKedarnath Balakrishnan, Jing Wang, Guanhao Shen
Life of this patent
Estimating the term…
Abstract
A memory controller includes an arbiter. The arbiter is configured to elevate a priority of memory access requests that generate row activate commands in response to receiving a same-bank refresh request, and to send a same-bank refresh command in response to receiving the same-bank refresh request.
Claims20
A memory controller, comprising:
- an arbiter implemented as a circuit configured to elevate a priority of memory access requests that generate row activate commands in response to receiving a same-bank refresh request, and to send a same-bank refresh command in response to receiving the same-bank refresh request.
A data processing system comprising:
- a data processor for generating memory access requests;
- and
- an arbiter implemented as a circuit configured to elevate a priority of the memory access requests that generate row activate commands in response to receiving a same-bank refresh request, and to send a same-bank refresh command in response to receiving the same-bank refresh request.
A method, comprising:
- storing memory access requests in a command queue;
- periodically generating same-bank refresh requests;
- selecting commands from the command queue and sending a same-bank refresh command to a memory interface in response to a same-bank refresh request;
- and
- elevating a priority of the memory access requests in the command queue that generate row activate commands in response to receiving the same-bank refresh request.
2 more elements
Dependencies are inferred from the claim text.