Back to results
US 12,118,241 B2Granted
Memory controller, memory system, and operating method thereof
AssigneeSK hynix Inc.
InventorDo Hun Kim
Life of this patent
Estimating the term…
Abstract
A memory controller includes a cache memory, a host control circuit, and a flash translation layer. The host control circuit receives a read command and a logical address from a host, reads out mapping information corresponding to the logical address from a buffer memory device, and caches the mapping information in the cache memory. The flash translation layer reads a physical address corresponding to the logical address from the mapping information cached in the cache memory.
Claims16
A memory controller, comprising:
- a cache memory;
- a buffer memory device storing logical-physical address mapping information loaded from a nonvolatile memory device;
- a host control circuit configured to receive a read command and a logical address from a host, issue a first command, in response to the read command, to read out mapping information corresponding to the logical address, from the buffer memory device when the mapping information corresponding to the logical address is cache-missed in the cache memory, and cache the mapping information from the buffer memory device in the cache memory;
- and
- a flash translation layer configured to receive the logical address from the host control circuit, and issue a second command to read a physical address corresponding to the logical address from the mapping information cached in the cache memory.
2 more elements
A method of operating a memory system, the method comprising:
- receiving, by a host control circuit, a read command and a logical address from a host;
- searching a cache memory for mapping information corresponding to the logical address;
- issuing a first command, in response to the read command, by the host control circuit when the mapping information corresponding to the logical address is cache-missed in the cache memory;
- reading the mapping information corresponding to the logical address, from a buffer memory device storing logical-physical address mapping information loaded from a nonvolatile memory device;
- caching the mapping information from the buffer memory device in the cache memory, in response to the first command, by the host control circuit;
- transferring the logical address from the host control circuit to a flash translation layer;
- issuing a second command, by the flash translation layer;
- and
- reading, by the flash translation layer, a physical address corresponding to the logical address from the mapping information cached in the cache memory, in response to the second command.
6 more elements
A memory system, comprising:
- a nonvolatile memory device;
- a buffer memory device configured to store logical-physical address mapping information loaded from the nonvolatile memory device;
- and
- a memory controller configured to control operations of the nonvolatile memory device and the buffer memory device,
- wherein the memory controller comprises:
- a cache memory;
- a host control circuit configured to receive a read command and a logical address from a host, issue a first command, in response to the read command, to read out mapping information corresponding to the logical address from the buffer memory device when the mapping information corresponding to the logical address is cache-missed in the cache memory, and cache the mapping information from the buffer memory device in the cache memory;
- and
- a flash translation layer configured to receive the logical address from the host control circuit, and issue a second command to read a physical address corresponding to the logical address from the mapping information cached in the cache memory.
6 more elements
Dependencies are inferred from the claim text.