Controller and persistent memory shared between multiple storage devices

An electronic system, comprising:

• two or more persistent storage devices;
• persistent memory outside of the two or more persistent storage devices;
• and
• a controller communicatively coupled to the persistent memory and the two or more persistent storage devices, the controller including integrated circuitry to:
• maintain first translation tables each for a respective one of the two or more persistent storage devices, wherein the first translation tables are to be maintained in the persistent memory, wherein the two or more persistent storage devices are each to comprise a different respective one of second translation tables, wherein the two or more persistent storage devices are each to comprise respective indirection circuitry to translate a respective logical block address (LBA) to a respective physical address, and wherein a first indirection granularity of each of the first translation tables is to be smaller than a second indirection granularity of each of the second translation tables,
• buffer write requests in the persistent memory in accordance with the first translation tables, wherein the write requests are each to target a respective one of the two or more persistent storage devices, and
• perform a sequential write from the persistent memory to a particular device of the two or more persistent storage devices when a portion of a buffer that corresponds to the particular device has an amount of data to write that corresponds to the second indirection granularity.

A method of controlling storage, comprising:

• maintaining first translation tables each for a respective one of two or more persistent storage devices, wherein the first translation tables are maintained in a persistent memory which is outside of the two or more persistent storage devices, wherein the two or more persistent storage devices each comprise a different respective one of second translation tables, wherein the two or more persistent storage devices each comprise respective indirection circuitry to translate a respective logical block address (LBA) to a respective physical address, and wherein a first indirection granularity of each of the first translation tables is smaller than a second indirection granularity of each of the second translation tables;
• buffering write requests in the persistent memory in accordance with the first translation tables, wherein the write requests are each to target a respective one of the two or more persistent storage devices;
• and
• performing a sequential write from the persistent memory to a particular device of the two or more persistent storage devices when a portion of a buffer that corresponds to the particular device has an amount of data to write that corresponds to the second indirection granularity.