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US 12,118,217 B2Granted
Memory system, memory controller and method for operating memory system, capable of determining target meta memory block on the basis of detected target state
AssigneeSK hynix Inc.
InventorJang Hun Yun
Life of this patent
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Abstract
In a memory system, one or more target meta memory blocks to which an entirety or a part of meta data is to be written are determined on the basis of a detected target state from among a plurality of target states. The one or more target meta memory block may be selected from among a plurality of meta memory blocks on the basis of a number of detected target states among the plurality of target states.
Claims15
A memory system comprising:
- a memory device including a plurality of meta memory blocks to which meta data is permitted to be written;
- and
- a memory controller configured to determine, based on a number of detected target states among a plurality of target states indicating operation of the memory device may be unstable, at least one of the plurality of meta memory blocks as a target meta memory block to which an entirety or a part of types of the meta data is to be written,
- wherein when the number of detected target states among the plurality of target states is equal to or greater than a first value, the memory controller determines:
- a first meta memory block among the plurality of meta memory blocks as a first target meta memory block in which the metadata of a master data type and a history data type are to be stored, and
- a second meta memory block among the plurality of meta memory blocks as a second target meta memory block in which the metadata of a map data type is to be stored.
3 more elements
A method for operating a memory system, comprising:
- determining a detected target state among a plurality of target states, indicating operation of the memory device may be unstable, set in advance;
- and
- determining at least one target meta memory block to which entirety or a part of types of meta data is to be written, among a plurality of meta memory blocks to which the meta data is permitted to be written, based on a number of detected target state,
- wherein determining the at least one target meta memory block comprises:
- when the number of detected target states among the plurality of target states is equal to or greater than a first value, determining:
- a first meta memory block among the plurality of meta memory blocks as a target meta memory block in which the metadata of a master data type and a history data type are to be stored, and
- a second meta memory block among the plurality of meta memory blocks as a target meta memory block in which the metadata of a map data type is to be stored.
4 more elements
A memory controller comprising:
- a memory interface capable of communicating with a memory device including a plurality of meta memory blocks to which meta data is permitted to be written;
- and
- a control circuit configured to determine, based on a number of detected target states among a plurality of target states which indicate operation of the memory device may be unstable, at least one of the plurality of meta memory blocks as a target meta memory block to which an entirety or a part of types of the meta data is to be written,
- wherein determining the at least one target meta memory block comprises:
- when the number of detected target states among the plurality of target states is equal to or greater than a first value, determining:
- a first meta memory block among the plurality of meta memory blocks as a target meta memory block in which the metadata of a master data type and a history data type are to be stored, and
- a second meta memory block among the plurality of meta memory blocks as a target meta memory block in which the metadata of a map data type is to be stored.
4 more elements
Dependencies are inferred from the claim text.