Configurable cryptographic processor with integrated DMA interface for secure data handling

A method of operating a processing system to transmit data via the processing system, the method comprising:

• storing data to be transmitted to a memory of the processing system;
• transferring the stored data via a first Direct-Memory-Access (DMA) channel from the memory to input data registers of a cryptographic co-processor;
• storing, by a plurality of input data registers of the cryptographic co-processor, a block of data having a plurality of bytes, the number of input data registers corresponding to a first number of registers;
• storing, by a plurality of output data registers of the cryptographic co-processor, a block of processed data, the number of output data registers corresponding to the first number of registers;
• storing first configuration data by a first programmable control register of the cryptographic co-processor;
• processing, by a cryptographic processing circuit of the cryptographic co-processor, the data stored in the input data registers as a function of the first configuration data stored in the first programmable control register;
• storing, by the cryptographic processing circuit, respective processed data to the output data registers;
• generating, by the cryptographic processing circuit, a first control signal in response to the processed data being stored in the output data registers;
• generating, by a first Direct-Memory-Access (DMA) interface circuit of the cryptographic co-processor, a first request signal requesting that a new block of data be transferred to the input data registers, the generating comprising:
• asserting the first request signal as a function of the first configuration data stored in the first programmable control register and in response to a synchronization signal, and
• de-asserting the first request signal in response to a first acknowledge signal;
• and
• generating, by a second DMA interface circuit of the cryptographic co-processor, a second request signal requesting that a block of processed data be transferred from the output data registers, the generating comprising:
• asserting the second request signal as a function of the first control signal,
• de-asserting the second request signal in response to a second acknowledge signal, and
• asserting the synchronization signal in response to the second acknowledge signal.

A device comprising a cryptographic processor, the cryptographic processor comprising:

• a plurality of input data registers configured to store a block of data having a plurality of bytes, the number of input data registers corresponding to a first number of registers;
• a plurality of output data registers configured to store a block of processed data, the number of output data registers corresponding to the first number of registers;
• a first programmable control register configured to store a first configuration data;
• a cryptographic processing circuit configured to:
• process the data stored in the input data registers as a function of the first configuration data stored in the first programmable control register,
• store respective processed data to the output data registers, and
• generate a first control signal in response to the processed data being stored in the output data registers;
• a first Direct-Memory-Access (DMA) interface circuit configured to generate a first request signal requesting that a new block of data be transferred to the input data registers, the first DMA interface circuit configured to:
• assert the first request signal as a function of the first configuration data stored to the first programmable control register and in response to a synchronization signal, and
• de-assert the first request signal in response to a first acknowledge signal;
• and
• a second DMA interface circuit configured to generate a second request signal requesting that a block of processed data be transferred from the output data registers, the second DMA interface circuit configured to:
• assert the second request signal as a function of the first control signal,
• de-assert the second request signal in response to a second acknowledge signal, and
• assert the synchronization signal in response to the second acknowledge signal.