Data processing unit with transparent root complex

Computing apparatus, comprising:

• a central processing unit (CPU);
• a root complex connected to the CPU and to a first peripheral component bus, which has a first address space and has at least a first downstream port for connection to at least one peripheral device, wherein the root complex is to present the at least one peripheral device to the CPU in the first address space;
• and
• switching logic, which has an upstream port for connection to a second downstream port on a second peripheral component bus of a host computer, the second peripheral component bus having a second address space, wherein the switching logic is connected to the root complex so that when a peripheral device is connected to the first downstream port on the first peripheral component bus, the switching logic presents the peripheral device to the host computer in the second address space of the second peripheral component bus.