Memory controller with pseudo-channel support
AssigneeAdvanced Micro Devices, Inc.
InventorsHideki Kanayama, YuBin Yao
Life of this patent
Estimating the term…
Abstract
A data processor accesses a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent for generating a memory access request, a memory controller for providing a memory command to the memory in response to a normalized request selectively using a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, and a data fabric for converting the memory access request into the normalized request selectively for the first pseudo channel and the second pseudo channel.
Claims20
A data processor for accessing a memory having a first pseudo channel and a second pseudo channel, comprising:
- at least one memory accessing agent for generating a memory access request;
- a memory controller for providing memory commands to the memory in response to a normalized request selectively using a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, wherein each of the first and second pseudo channel pipeline circuits re-orders and prioritizes accesses based on particular access patterns in its respective pseudo channel;
- a data fabric coupled between said at least one memory accessing agent and said memory controller for converting said memory access request into said normalized request selectively for said first pseudo channel pipeline circuit and said second pseudo channel pipeline circuit;
- and
- a serializer that is operable to serialize memory commands from said first pseudo channel pipeline circuit and said second pseudo channel pipeline circuit.
A memory controller for providing memory commands to a physical interface circuit for a memory having a first pseudo channel and a second pseudo channel, comprising:
- a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, each comprising:
- a front-end interface circuit for receiving normalized addresses of a respective one of the first pseudo channel and the second pseudo channel, where in the normalized addresses do not indicate a pseudo channel, for converting said normalized addresses into decoded addresses of decoded memory access requests;
- a command queue coupled to said front-end interface circuit for storing said decoded memory access requests;
- and
- an arbiter for selecting among said decoded memory access requests from said command queue according to predetermined criteria and providing selected memory access requests to an output thereof, and
- a serializer that is operable to serialize memory commands from said first pseudo channel pipeline circuit and said second pseudo channel pipeline circuit,
- wherein each of the first and second pseudo channel pipeline circuits re-orders and prioritizes accesses based on particular access patterns in its respective pseudo channel.
A method for a data processor to provide commands to a memory that has a first pseudo channel and a second pseudo channel, comprising:
- generating memory access requests;
- routing said memory access requests selectively between upstream ports and downstream ports of a data fabric, and memory access responses selectively between said downstream ports and said upstream ports of said data fabric;
- decoding said memory access requests in said data fabric according to one of a plurality of pseudo channels including the first pseudo channel and the second pseudo channel based on a pseudo channel address of said memory access request;
- processing first memory access requests of said first pseudo channel in a first decoding and command arbitration circuit;
- processing second memory access requests of said second pseudo channel in a second decoding and command arbitration circuit,
- wherein processing said first memory access requests and processing said second memory access requests comprise re-ordering and prioritizing accesses based on particular access patterns in each respective pseudo channel;
- and
- providing memory commands to the memory based on serializing memory commands processed by said first decoding and command arbitration circuit and memory commands processed by said second decoding and command arbitration circuit.
Dependencies are inferred from the claim text.