Techniques for supporting large frame buffer apertures with better system compatibility
AssigneeAdvanced Micro Devices, Inc.
InventorPaul Blinzer
Life of this patent
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Abstract
A technique for accessing accelerated processing device (“APD”) memory is provided. The technique includes identifying whether to activate one or both of a first direct mapping unit and a second direct mapping unit, wherein the first direct mapping unit is associated with a small address size and the second direct mapping unit is associated with a large address size; activating the identified one or both of the first direct mapping unit and the second direct mapping unit; and accessing memory of the accelerated processing device using the one or both of the first direct mapping unit and the second direct mapping unit.
Claims20
A method for accessing accelerated processing device (“APD”) memory, the method comprising:
- for a first set of memory addresses provided via a small address base address register of the APD, mapping the first set of memory addresses to a first portion of a memory of the APD in a tiled manner, wherein the small address base address register is configured to be accessed with addresses of a first size;
- accessing the memory of the APD according to the first mapping and the first set of memory addresses, wherein the accessing includes accessing in the tiled manner, in which a first address of the first set of memory addresses maps to an end of a tile in the memory of the APD and in which a second address immediately subsequent to the first address maps to a beginning of the tile;
- for a second set of memory addresses provided via a large address base address register of the APD, mapping the second set of memory addresses to a second portion of the memory of the APD, wherein the second portion is larger than the first portion, wherein the large address base address register is configured to be accessed with addresses of a second size that is larger than the first size;
- and accessing the memory of the APD according to the second mapping and the second set of memory addresses.
A computing device, comprising:
- one or more memories configured to store instructions;
- and a processor configured to execute the instructions to access accelerated processing device (“APD”) memory, by:
- for a first set of memory addresses provided via a small address base address register of the APD, map the first set of memory addresses to a first portion of a memory of the APD in a tiled manner, wherein the small address base address register is configured to be accessed with addresses of a first size;
- access the memory of the APD according to the first mapping and the first set of memory addresses, wherein the accessing includes accessing in the tiled manner, in which a first address of the first set of memory addresses maps to an end of a tile in the memory of the APD and in which a second address immediately subsequent to the first address maps to a beginning of the tile;
- for a second set of memory addresses provided via a large address base address register of the APD, map the second set of memory addresses to a second portion of the memory of the APD, wherein the second portion is larger than the first portion, wherein the large address base address register is configured to be accessed with addresses of a second size that is larger than the first size;
- and access the memory of the APD according to the second mapping and the second set of memory addresses.
A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform operations comprising:
- for a first set of memory addresses provided via a small address base address register of an accelerated processing device (“APD”), map the first set of memory addresses to a first portion of a memory of the APD in a tiled manner, wherein the small address base address register is configured to be accessed with addresses of a first size;
- access the memory of the APD according to the first mapping and the first set of memory addresses, wherein the accessing includes accessing in the tiled manner, in which a first address of the first set of memory addresses maps to an end of a tile in the memory of the APD and in which a second address immediately subsequent to the first address maps to a beginning of the tile;
- for a second set of memory addresses provided via a large address base address register of the APD, map the second set of memory addresses to a second portion of the memory of the APD, wherein the second portion is larger than the first portion, wherein the large address base address register is configured to be accessed with addresses of a second size that is larger than the first size;
- and access the memory of the APD according to the second mapping and the second set of memory addresses.
Dependencies are inferred from the claim text.