Method and apparatus for performing data access management of memory device in predetermined communications architecture with aid of unbalanced table update

A memory controller of a memory device, the memory device comprising the memory controller and a non-volatile (NV) memory, the NV memory comprising at least one NV memory element, the at least one NV memory element comprising a plurality of blocks, the memory controller comprising:

• a processing circuit, arranged to control the memory controller according to a plurality of host commands from a host device, to allow the host device to access the NV memory through the memory controller, wherein the processing circuit is arranged to perform data access management of the memory device in a predetermined communications architecture with aid of unbalanced table update;
• and
• a transmission interface circuit, arranged to perform communications with the host device;
• wherein:
• the memory controller receives the plurality of host commands from the host device through the transmission interface circuit of the memory controller, receives a set of first data and a set of second data with a first active block and a second active block among the plurality of blocks according to a set of first commands and a set of second commands among the plurality of host commands, respectively, and updates a first temporary physical-to-logical (P2L) address mapping table corresponding to the first active block and a second temporary P2L address mapping table corresponding to the second active block, wherein the set of first commands and the set of second commands indicate that writing the set of first data into the memory device and writing the set of second data into the memory device are requested, respectively;
• and
• in response to a table region of any temporary P2L address mapping table among the first temporary P2L address mapping table and the second temporary P2L address mapping table being full, the memory controller updates a first P2L address mapping table in the NV memory according to the first temporary P2L address mapping table and selectively updates a second P2L address mapping table in the NV memory according to the second temporary P2L address mapping table, for performing subsequent processing, wherein the first temporary P2L address mapping table and the second temporary P2L address mapping table are arranged to occupy a first table region of a first size and a second table region of a second size in a Random Access Memory (RAM) within the memory controller, respectively.