Semiconductor system

A semiconductor system comprising:

• a controller configured to:
• output a command and first and second addresses for performing a read modify write operation when the first and second addresses have a logic level combination for selecting contiguous regions, and
• output first data;
• and
• a semiconductor device configured to:
• store, as write data, the first data in a data storage circuit during the read modify write operation based on the command,
• output second internal data that has been stored in at least a memory cell of a core circuit that is selected based on the command and the second address after outputting first internal data that has been stored in at least a memory cell of the core circuit that is selected based on the command and the first address,
• generate parities by performing an error correction code (ECC) operation based on the first and second internal data and the write data, and
• store the write data and the parities in at least a memory cell of the core circuit that is selected by the first address.

A semiconductor system comprising:

• a controller configured to:
• output first and second chip selection signals, a command address, and first data, and
• receive second and third data;
• a first semiconductor device configured to:
• perform a read modify write operation based on a logic level combination of the command address when the first chip selection signal is enabled,
• store the first data as write data,
• output first and second internal data that have been stored in at least a memory cell that is selected by the command address in a read operation of the read modify write operation,
• generate a first parity by performing an error correction code (ECC) operation based on the first and second internal data and the write data,
• store the write data and the first parity in a write operation of the read modify write operation, and
• output the first and second internal data as the second data by serializing the first and second internal data;
• and
• a second semiconductor device configured to:
• perform a normal operation based on a logic level combination of the command address when the second chip selection signal is enabled,
• store third internal data that is generated from the first data in at least a memory cell that is selected by the command address in a write operation of the normal operation, and
• output fourth internal data as the third data by correcting an error of the fourth internal data based on the fourth internal data and a second parity that have been stored in at least a memory cell that is selected by the command address in a read operation of the normal operation.

An operating method of a memory apparatus, the operating method comprising:

• consecutively reading, in response to a read-modify-write (RMW) command, a sequence of data pieces respectively from neighboring memory cell regions indicated by respective addresses provided together with the RMW command, the memory cell regions being within the memory apparatus;
• and
• storing, at least in a part of the regions, write data together with parity data that is generated on a basis of the write data and the data pieces, the write data being provided together with the RMW command,
• wherein, the respective addresses for performing a read operation have a logic level combination for selecting the neighboring memory cell regions.