Methods and apparatus to reduce display connection latency

An apparatus to reduce display connection latency, the apparatus comprising:

• graphics circuitry configured to, in response to first instructions from processor circuitry to enter a low power state, power off,
• power-island circuitry configured to, in response to the first instructions from the processor circuitry to enter the low power state, receive power from an auxiliary power source;
• connector circuitry configured to generate a wake signal in response to a display being plugged into a port;
• the power-island circuitry including a Schmitt Trigger and configured to, while in the low power state:
• filter the wake with the Schmitt trigger;
• and
• request, based on the filtered wake signal, access to a high power state;
• and
• the graphics circuitry configured to:
• exit, in response to second instructions from the processor circuitry, the low power state by powering on;
• and
• communicate, in response to exiting the low power state, with the display to obtain an identification.

A non-transitory computer readable medium comprising instructions that, when executed, causes at least one processor to at least:

• cause discrete circuitry to enter a low power state where graphics circuitry within the discrete circuitry is powered off and power-island circuitry within the discrete circuitry is powered on;
• receive an indication while the discrete circuitry is in the low power state, the indication provided by the power-island circuitry, the indication based on a wake signal that is generated by connector circuitry and filtered by a Schmitt Trigger when a display is plugged into a port;
• in response to the indication, cause the discrete circuitry to exit the low power state;
• and
• the graphics circuitry configured to, in response to the discrete circuitry exiting the low power state, communicate with the display to obtain an identification.

A method to reduce display connection latency, the method comprising:

• causing, by processor circuitry, display circuitry to enter a low power state where graphics circuitry within the display circuitry is powered off and power-island circuitry within the display circuitry is powered on;
• generating, by connector circuitry, a wake signal in response to a display being plugged into a port;
• filtering, while the display circuitry is in the low power state and by a Schmitt Trigger, the wake signal;
• causing, by the processor circuitry and based on the filtered wake signal, discrete circuitry to exit the low power state;
• and
• communicating, by the graphics circuitry and in response to the discrete circuitry exiting the low power state, with the display to obtain an identification.