SOC for operating plural NPUS according to plural clock signals having multi-phases

A system comprising:

• a substrate;
• a first semi-conductor chip, mounted on the substrate, provided for a first NPU configured to perform operations of an artificial neural network (ANN) model;
• a second semi-conductor chip, mounted on the substrate, provided for a second NPU configured to perform operations of an ANN model;
• and
• a clock signal supply circuit, mounted on the substrate, configured to output one or more clock signals,
• wherein each of the first NPU and the second NPU includes a plurality of processing elements (PEs), and the plurality of PEs include an adder, a multiplier, and an accumulator,
• wherein a first clock signal among the one or more clock signals, is supplied to the first NPU, and a second clock signal among the one or more clock signals, is supplied to the second NPU,
• wherein at least one of the first and second clock signals has a preset phase based on a phase of an original clock signal, and
• wherein the first NPU is configured to operate based on a first phase of the first clock signal, and the second NPU is configured to operate based on a second phase of the second clock signal so that two NPUs including the first NPU and the second NPU operate distributedly in different two phases including the first phase and second phase to reduce a peak power,
• wherein a phase difference between the first and second clock signals is determined in consideration of a peak power of the system.

A method of operating a plurality of neural processing units (NPU), comprising:

• generating a plurality of clock signals including a first clock signal and a second clock signal;
• and
• operating a first NPU based on a first phase of the first clock signal while operating a second NPU based on a second phase of the second clock signal so that two NPUs including the first NPU and the second NPU operate distributedly in different two phases including the first phase and second phase,
• wherein each of the first NPU and the second NPU includes a plurality of processing elements (PEs), and each processing element includes an adder, a multiplier, and an accumulator,
• wherein at least one of the first and second clock signals has a preset phase based on a phase of an original clock signal to reduce a peak power,
• wherein a phase difference between the first and second clock signals is determined in consideration of a peak power of the system.