Method of determining overlay error during semiconductor fabrication

A method of determining an overlay error during a semiconductor fabrication, comprising:

• forming a first structural layer deposited over a wafer, the first structural layer comprising first patterned structures and a target feature;
• forming a second structural layer deposited over the first structural layer, the second structural layer comprising second patterned structures correspondingly over the first patterned structures, a first axis, a second axis and a pair of alignment features, wherein the pair of alignment features are disposed at the first and the second axes, wherein an intersection of the first and second axes is deposited correspondingly over the target feature;
• and
• determining a relative displacement of the first and second structural layers using a position of the first axis relative to the target feature and a position of the second axis relative to the target feature.