FeRAM decoupling capacitor

A method comprising:

• forming an access transistor in a memory region of a substrate, and forming a transistor contact having a bottom surface physically contacting the access transistor and being embedded in a first dielectric layer, the first dielectric layer also surrounding a portion of the access transistor;
• forming an interconnect structure over the access transistor, the interconnect structure continuing across through a first region over the substrate, the first region being a different region than the memory region, the interconnect structure comprising:
• a first metallization layer embedded within a first inter-metal dielectric (IMD) layer, the first metallization layer being above and in physical contact with a topmost surface of the transistor contact, the first IMD layer being above a topmost surface of the first dielectric layer;
• a second metallization layer embedded within a second IMD layer, the second IMD layer being above a topmost surface of the first IMD layer;
• forming a first ferroelectric random access memory (FeRAM) memory element disposed in the memory region in a third IMD layer of the interconnect structure, the third IMD layer being different from the first IMD layer, the first FeRAM memory element including a bottom electrode having a bottommost surface that is above a topmost surface of the first metallization layer and having a top electrode having a topmost surface that is below a bottommost surface of the second metallization layer, the FeRAM being electrically coupled to the access transistor;
• while forming the first FeRAM memory element, simultaneously forming one or more metal-ferroelectric insulator-metal (MFM) capacitors disposed in the first region in the first IMD layer, the one or more MFM capacitors each having a same structure as the first FeRAM memory element;
• and
• coupling a first capacitor of the one or more MFM capacitors to a device disposed over the substrate.

A method comprising:

• forming an interconnect over a substrate, the interconnect extending over a memory access transistor disposed in the substrate and over a logic component disposed in the substrate;
• forming a first metallization layer, the first metallization layer being embedded with a first dielectric layer, the first dielectric layer having a planar topmost surface;
• depositing a bottom electrode on the planar topmost surface of the first dielectric layer, the bottom electrode being planar across its full extent, and being over and coupled to a first metallization layer of the interconnect;
• depositing a first insulating layer over the bottom electrode, the first insulating layer comprising a ferroelectric insulating material, the first insulating layer being planar across its full extent;
• depositing a top electrode over the first insulating layer the top electrode being planar across its full extent;
• separating the bottom electrode, the first insulating layer, and the top electrode into a first capacitor, a second capacitor, and a third capacitor, each of the first capacitor, second capacitor, and third capacitor comprising respective portions of the bottom electrode, the first insulating layer, and the top electrode;
• depositing a second insulating layer over and laterally surrounding the first capacitor, the second capacitor, and the third capacitor, the second insulating layer comprising a different material composition than the ferroelectric insulating material, wherein the first capacitor is electrically coupled to the memory access transistor;
• and
• depositing a second metallization layer over the second insulating layer, wherein portions of the second metallization layer are coupled to the top electrode of each of the first capacitor, the second capacitor, and the third capacitor, wherein the third capacitor is electrically coupled to the logic component.