Capping layer over FET FeRAM to increase charge mobility
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsRainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
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Abstract
In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode over a substrate, and a gate dielectric layer arranged over the gate electrode. The gate dielectric layer includes a ferroelectric material. An active structure is arranged over the gate dielectric layer and includes a semiconductor material. A source contact and a drain contact are arranged over the active structure. A capping structure is arranged between the source and drain contacts and over the active structure. The capping structure includes a first metal material.
Claims20
An integrated chip, comprising:
- a gate electrode arranged over a substrate;
- a gate dielectric layer arranged over the gate electrode and comprising a ferroelectric material;
- an active structure arranged over the gate dielectric layer and comprising a semiconductor material;
- a source contact and a drain contact arranged over the active structure;
- and
- a capping structure arranged over the active structure and between the source contact and the drain contact, wherein the capping structure comprises a first layer comprising a first metal material and a second layer arranged over the first layer and comprising a second metal material.
An integrated chip, comprising:
- a gate electrode arranged over a substrate;
- a gate dielectric layer arranged over the gate electrode and comprising a ferroelectric material;
- an active structure arranged over the gate dielectric layer and comprising a semiconductor material;
- a source contact and a drain contact arranged over the active structure;
- and
- a capping structure arranged over the active structure and between the source contact and the drain contact;
- wherein the active structure comprises a plurality of metal oxides, which includes a first metal oxide having a highest bond energy amongst the plurality of metal oxides, and further comprises a layer of the first metal oxide separating a remainder of the active structure from the capping structure.
An integrated chip, comprising:
- a gate electrode over a substrate;
- a gate dielectric layer over the gate electrode;
- a multilayer stack over the gate dielectric layer and comprising a plurality of zinc oxide layers and a plurality of cocktails layers, wherein the cocktails layers are alternatingly stacked with the zinc oxide layers and individually comprise a mixture of gallium oxide and indium oxide;
- a source contact and a drain contact over the multilayer stack;
- and
- a capping structure over the multilayer stack and between the source contact and the drain contact, wherein the capping structure comprises aluminum and calcium.
Dependencies are inferred from the claim text.