Integrated circuit device

An integrated circuit device comprising:

• a substrate;
• a peripheral circuit structure disposed on the substrate, wherein the peripheral circuit structure includes a peripheral circuit and a lower wiring connected to the peripheral circuit;
• a cell array structure overlapping the peripheral circuit structure in a vertical direction, wherein the cell array structure includes a memory stack that includes a plurality of gate lines stacked in the vertical direction and a channel structure passing through the plurality of gate lines in the vertical direction;
• a conductive plate disposed between the peripheral circuit structure and the cell array structure;
• a through hole via passing through the cell array structure wherein the through hole via extends to an inner portion of the peripheral circuit structure to be connected to the lower wiring, outside the conductive plate;
• and
• an etch guide member disposed outside the conductive plate at the same level as the conductive plate, wherein:
• wherein the conductive plate is configured to transfer a common source voltage to the memory stack,
• the etch guide member has the same thickness as a thickness of the conductive plate, and includes the same material as the conductive plate, with the through hole via therebetween;
• wherein the etch guide member penetrates into the through hole via in a horizontal direction;
• and
• wherein the through hole via is disposed between the etch guide member and the conductive plate and contacts the etch guide member on a first side of the through hole via and wherein the through hole via contacts the insulation layer on a second side of the through hole via opposite to the first side.

An integrated circuit device comprising:

• a substrate;
• a peripheral circuit structure disposed on the substrate, wherein the peripheral circuit structure includes a peripheral circuit and a plurality of lower wiring layers connected to the peripheral circuit;
• a cell array structure overlapping the peripheral circuit structure in a vertical direction, wherein the cell array structure includes a memory stack that includes a plurality of gate lines stacked and a channel structure passing through the plurality of gate lines in the vertical direction, wherein the cell array structure further includes an insulation layer surrounding the memory stack, and a plurality of upper wiring layers disposed on the channel structure;
• a plate common source line disposed between the peripheral circuit structure and the cell array structure;
• a through hole via passing through the insulation layer, wherein the through hole via extends to an inner portion of the peripheral circuit structure to be connected up to an uppermost layer of the plurality of lower wiring layers from a lowermost layer of the plurality of upper wiring layers;
• and
• an etch guide member disposed outside the plate common source line, wherein:
• the etch guide member is disposed at the same level as the plate common source line, has the same thickness as a thickness of the plate common source line, and includes the same material as a material of the plate common source line, and
• wherein the through hole via is disposed between the etch guide member and the conductive plate and contacts the etch guide member on a first side of the through hole via and wherein the through hole via contacts the insulation layer on a second side of the through hole via opposite to the first side.