Integrated chip including a tunnel dielectric layer which has different thicknesses over a protrusion region of a substrate

An integrated chip, comprising:

• a first source/drain region disposed in a substrate;
• a second source/drain region disposed in the substrate and spaced apart from the first source/drain region;
• wherein a first cross-sectional plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region;
• a gate electrode extending over a channel region in the substrate between the first source/drain region and the second source/drain region;
• and
• a dielectric layer disposed over the channel region and separating the channel region from the gate electrode;
• and
• wherein the channel region has a channel width measured in a second cross-sectional plane that is perpendicular to the first cross-sectional plane, the channel region had a curved, convex upper surface in the second cross-sectional plane, and the dielectric layer has different thicknesses measured normal to the curved, convex upper surface at different respective points along the channel width, wherein the dielectric layer has a width larger than the channel width in the second cross-sectional plane.

An integrated chip, comprising:

• a gate electrode extending over an upper surface of a substrate, the gate electrode separated from the upper surface of the substrate by way of a dielectric structure;
• wherein the gate electrode extends along a first plane between inner sidewalls of an isolation structure arranged within the substrate and extends along a second plane between a first source/drain region and a second source/drain region, the second plane being perpendicular to the first plane;
• and
• wherein the dielectric structure has a first thickness and a second thickness measured along the first plane, the first thickness measured normal from an outer sidewall of the substrate directly below the gate electrode to a corresponding outer sidewall of the dielectric structure and the second thickness measured normal from an upper surface of the substrate directly below the gate electrode and a corresponding upper surface of the dielectric structure, the second thickness being less than the first thickness, and wherein the dielectric structure is disposed above the isolation structure when viewed from a cross section defined by the first plane.