Integrated structures and methods of forming vertically-stacked memory cells

A method of forming vertically-stacked memory cells, comprising:

• forming an opening through a stack of alternating silicon dioxide levels and conductively-doped silicon levels;
• the opening having insulative sidewalls along the silicon dioxide levels and conductive sidewalls along the conductively-doped silicon levels;
• performing a selective etch to selectively remove the conductively-doped silicon relative to the silicon dioxide, the selective etch forming cavities extending into the conductively-doped silicon levels to form recessed concave conductive sidewalls along the conductively-doped silicon levels, regions of the silicon dioxide levels remaining as ledges which separate adjacent cavities from one another, the ledges extending from the recessed concave conductive sidewalls to the insulative sidewalls;
• removing silicon dioxide from the ledges to form thinned ledges extending from the recessed concave conductive sidewalls, an entirety of the thin ledges being curved;
• after the removing the silicon dioxide from the ledges, forming charge-blocking dielectric and charge-storage structures within the cavities;
• forming gate dielectric along the charge-storage structures;
• and
• forming channel material along the gate dielectric.