3D memory semiconductor device and structure

A 3D memory device, the device comprising:

• a first vertical pillar, said first vertical pillar comprises a transistor source;
• and
• a second vertical pillar, said second vertical pillar comprises a transistor drain,
• wherein said first vertical pillar and said second vertical pillar each comprises a source or a drain for a first plurality of self-aligned overlaying horizontally-oriented memory transistors,
• wherein at least of one of said first plurality of self-aligned overlaying horizontally-oriented memory transistors is disposed between said first vertical pillar and said second vertical pillar,
• wherein said first plurality of self-aligned overlaying horizontally-oriented memory transistors each comprise a self-aligned gate,
• wherein each self-aligned gate is disposed atop of a self-aligned underlying gate,
• wherein each of said first plurality of self-aligned overlaying horizontally-oriented memory transistors comprises a self-aligned channel region,
• wherein at least two of the self-aligned channel region of said first plurality of self-aligned horizontally-oriented memory transistors comprise direct connection,
• wherein said first plurality of self-aligned overlaying horizontally-oriented memory transistors each comprise a tunneling oxide region and a self-aligned charge trap region, and
• wherein said tunneling oxide region is thinner than 1 nm or does not exist, which enables said 3D memory device to operate at high speed.

A 3D memory device, the device comprising:

• a first vertical pillar, said first vertical pillar comprises a transistor source;
• and
• a second vertical pillar, said second vertical pillar comprises a transistor drain,
• wherein said first vertical pillar and said second vertical pillar each comprises a source or a drain for a first plurality of self-aligned overlaying horizontally-oriented memory transistors,
• wherein at least of one of said first plurality of self-aligned overlaying horizontally-oriented memory transistors is disposed between said first vertical pillar and said second vertical pillar,
• wherein said first plurality of self-aligned overlaying horizontally-oriented memory transistors each comprise a self-aligned gate,
• wherein each self-aligned gate is disposed atop of a self-aligned underlying gate,
• wherein each of said first plurality of self-aligned overlaying horizontally-oriented memory transistors comprises a self-aligned channel region,
• wherein at least two of the self-aligned channel region of said first plurality of self-aligned overlaying horizontally-oriented memory transistors comprise direct connection, and
• wherein said first vertical pillar comprises metal and does not comprise n+ type doped silicon.