Vertical access line in a folded digitline sense amplifier

An apparatus, comprising:

• an array of memory cells, wherein
• each memory cell is formed within four lithographic features squared (4F2) according to a folded digitline sense amplifier architecture;
• the memory cells include alternately angled active areas having adjacent access devices, each access device having a first source/drain region and a second source/drain region separated by a channel region and a gate opposing the channel region;
• a pair of adjacent memory cells share a digitline contact at the respective second source/drain regions and a each respective storage node of the pair of adjacent memory cells is coupled to the respective first source/drain regions;
• and
• the gate is connected to vertically oriented access lines formed on opposing side of a depletion region to each access device;
• a sense amplifier coupled to digitlines in the array;
• and
• an insulator material formed between adjacent digitlines to separate adjacent memory cells.

An apparatus, comprising:

• a memory cell having a size of four lithographic features squared (4F2);
• wherein the memory cell includes a vertical gate opposing a channel region;
• wherein the channel region is coupled a storage node at first source/drain region and is coupled to a digitline at a second source/drain region;
• wherein an active area of the memory cell is at an angle between 20° and 65° with respect to the digitline;
• wherein an insulator material isolates the memory cell from an adjacent memory cell;
• and
• wherein the memory cell is coupled to the digitline having a folded digitline sense amplifier architecture.