Method of making of plurality of 3D vertical logic elements integrated with 3D memory

A method of fabricating a memory device including a transistor, the method comprising:

• forming a stack of layers for the transistor including:
• a first source/drain structure of the transistor;
• a gate structure of the transistor, the gate structure being above the first source/drain structure and extending horizontally;
• and
• a second source/drain structure of the transistor, each of the structures separated from each other by at least one dielectric;
• forming a cavity through the stack of layers;
• forming a semiconductor material in a first portion of the cavity, the semiconductor material extending from the first source/drain structure to the second source/drain structure;
• and
• forming a capacitor electrically coupled to and extending from the transistor in a second portion of the cavity.

A system comprising:

• a column extending from a substrate, the column comprising:
• a transistor having a channel extending vertically along the column;
• a capacitor substantially vertically aligned with the transistor and having a length that is greater than a width of the capacitor, the capacitor including:
• a first metal part in electrical contact with the transistor and defining an interior cavity;
• a second metal part at least partly disposed inside of the interior cavity of the first metal part and in an electrical contact with an electrical common or a ground, the first metal part oriented vertically aligned with the transistor;
• and
• a layer of electrically insulating material disposed inside the interior cavity in between the first metal part and the second metal part.