US 12,114,479 B2 · Three-dimensional memory arrays with layer selector transistors

Abstract

A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

Claims20

Dependent claims

An integrated circuit (IC) device, comprising:

an arrangement that includes two or more memory cells, a transistor, and a bitline;
and
an interconnect structure,
wherein:
an individual memory cell of the arrangement includes an access transistor,
each of the transistor and the access transistor includes a first region and a second region, wherein one of the first region and the second region is a source region and another one of the first region and the second region is a drain region,
the first regions of the access transistors of the two or more memory cells of the arrangement are directly electrically connected to one another and to the bitline, and the bitline is directly electrically connected to the first region of the transistor, and
the second region of the transistor is directly electrically connected to the interconnect structure.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/368,329Filed 6 Jul 2021 · continuation

Priority

20 Nov 2019

Published

US 2021/0151438 A128 Oct 2021

Granted

8 Oct 2024

Term ends

Not estimatedThe source records don’t support an estimate.

Classification16 codes

G11C 11/404
With charge regeneration common to a multiplicity of memory cells, i.e. external refresh: with one charge-transfer gate, e.g. MOS transistor, per cell
H10B 12/31
DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells: having a storage electrode stacked over the transistor
G11C 5/063
Arrangements for interconnecting storage elements electrically, e.g. by wiring: voltage and signal distribution in integrated semi-conductor…
G11C 11/4045
With one charge-transfer gate, e.g. MOS transistor, per cell: using a plurality of serially connected access transistors, each having a storage…

Family

Application16/689,789Parent of this continuation · filed 20 Nov 2019

US 2021/0335791 A1Pre-grant publication · published 28 Oct 2021

US 11,139,300 B2Parent of this continuation

US 2021/0151438 A1Published application

US 12,114,479 B2This patent

From the US filing history. Foreign family members aren’t listed.

Three-dimensional memory arrays with layer selector transistors

Life of this patent

Three-dimensional memory arrays with layer selector transistors

Life of this patent

Abstract

Claims20