Three-port SRAM cell and layout method

A semiconductor device, comprising:

• a three-port memory cell, comprising:
• a write port circuit configured to perform a write function according to a write word line, a first write bit line and a second write bit line, and comprising:
• a first write pass-gate transistor and a first write pull-up transistor coupled in series between a supply voltage and the first write bit line;
• and
• a second write pass-gate transistor and a second write pull-up transistor coupled in series between the supply voltage and the second write bit line;
• a first read port circuit comprising a first read pass-gate transistor and a first read pull-down transistor connected in series between a ground and a first read bit line, and configured to perform a first read function according to a first read word line;
• a second read port circuit comprising a second read pass-gate transistor and a second read pull-down transistor connected in series between the ground and a second read bit line, and configured to perform a second read function according to a second read word line;
• and
• a first gate structure, a second gate structure, a third gate structure and a fourth gate structure extending in a second direction,
• wherein the first and second read pass-gate transistors and the first and second read pull-down transistors share a first active structure extending in a first direction, the first and second write pass-gate transistors share a second active structure extending in the first direction, and the first and second write pull-up transistors share a third active structure extending in the first direction, and the second active structure is disposed between the first and third active structures,
• wherein the first read bit line and the second read bit line extend in the first direction in a first metallization layer over the first active structure, and the first write bit line and the second write bit line extend in the first direction in a second metallization layer over the first metallization layer,
• wherein the first, second, third and fourth gate structures form channel regions of the first read pass-gate transistor, the first read pull-down transistor, the second read pull-down transistor, and the second read pass-gate transistor, respectively,
• wherein the first write pull-up transistor and the first read pull-down transistor share the second gate structure, and the second write pull-up transistor and the second read pull-down transistor share the third gate structure.

A method for manufacturing a semiconductor device, comprising:

• forming a three-port memory cell, wherein the three-port memory cell comprises:
• a write port circuit;
• a first read port circuit comprising a first read pass-gate transistor and a first read pull-down transistor connected in series;
• and
• a second read port circuit comprising a second read pass-gate transistor and a second read pull-down transistor connected in series,
• wherein the first and second read pass-gate transistors and the first and second read pull-down transistors share a first active structure extending in a first direction;
• forming a first read bit line and a second read bit line that extend in the first direction in a first metallization layer over the first active structure;
• forming a write word line that extends in a second direction in a second metallization layer over the first metallization layer;
• forming a first write bit line and a second write bit line that extend in the first direction in a third metallization layer over the second metallization layer;
• forming a first read word line and a second read word line that extend in the second direction in a fourth metallization layer over the third metallization layer;
• and
• forming a first VSS conductor that extends in the first direction in the first metallization layer,
• wherein the first VSS conductor is adjacent the second read bit line,
• wherein the second read bit line is disposed between the first VSS conductor and the first read bit line or the first VSS conductor is disposed between the first and second read bit lines,
• wherein the write port circuit is configured to perform a write function according to the write word line, the first write bit line and the second write bit line,
• wherein the first read port circuit is configured to perform a first read function according to the first read bit line and the first read word line, and the second read port circuit is configured to perform a second read function according to the second read bit line and the second read word line.