Dual gain column structure for column power area efficiency

A method of operating a pixel cell readout circuit, comprising:

• selectively coupling each of a low conversion gain (LCG) second input transistor and a high conversion gain (HCG) second input transistor of a comparator to a current mirror of the comparator;
• coupling a gain network between a gate node of a first input transistor of the comparator and a ramp generator output, wherein the gain network is configured to provide a variable comparator gain to the comparator;
• coupling an LCG auto-zero switch between a drain node and a gate node of the LCG second input transistor, wherein the gate node of the LCG second input transistor is further selectively coupled to a bitline;
• coupling an HCG auto-zero switch between a drain node and a gate node of the HCG second input transistor, wherein the gate node of the HCG second input transistor is further selectively coupled to the bitline;
• prior to an LCG reset period,
• turning on and off the LCG auto-zero switch;
• and
• prior to an HCG reset period,
• turning on and off the HCG auto-zero switch.

A pixel cell readout circuit, comprising:

• a comparator having a first input transistor and a second input transistor;
• a gain network coupled between a gate node of the first input transistor and a ramp generator output, wherein the gain network is configured to provide a variable comparator gain to the comparator;
• a first capacitor coupled between a gate node of the second input transistor and a bitline;
• and
• a second capacitor coupled between the gate node of the second input transistor and an auto-zero voltage source,
• wherein the auto-zero voltage source is configured to be at a low level during a low conversion gain (LCG) reset period and an LCG signal readout period, and
• wherein the auto-zero voltage source is configured to be at a high level during a high conversion gain (HCG) reset period and an HCG signal readout period.

A method of operating a pixel cell readout circuit, comprising:

• coupling a gain network between a gate node of a first input transistor of a comparator and a ramp generator output, wherein the gain network is configured to provide a variable comparator gain to the comparator;
• coupling a first capacitor between a gate node of a second input transistor of the comparator and a bitline;
• coupling a second capacitor between the gate node of the second input transistor and an auto-zero voltage source;
• during a low conversion gain (LCG) reset period,
• configuring the auto-zero voltage source to be at a low level;
• during a high conversion gain (HCG) reset period,
• configuring the auto-zero voltage source to be at a high level;
• during an HCG signal readout period,
• configuring the auto-zero voltage source to be at the high level;
• and
• during an LCG signal readout period,
• configuring the auto-zero voltage source at the low level.