Pixel output parasitic capacitance reduction and predictive settling assist
AssigneeApple Inc.
InventorsHai Yan, Chiajen Lee
Life of this patent
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Abstract
Disclosed herein are electronic devices and image sensors containing pixel arrays, layouts of electrical signal lines for such pixel arrays, and methods of pixel read out operations, including row read operations, for such pixel arrays. Layouts are disclosed that have reduced sets of shielding or ground lines. In some layouts, shielding ground lines are used only between pairs of adjacent pixel output signal lines (OSLs). Also disclosed is a method of using one OSL within a pair of adjacent pixel OSLs to provide settling assist of the pixel output signal on the other OSL of the adjacent pair of OSLs.
Claims20
A method of performing a row read operation of a pixel array of an image sensor, the pixel array including at least a first and a second pixel column, a first and a second pair of adjacent output signal lines (OSLs) positioned with or between and parallel to the first and second pixel columns, a first ground line interposed between the first and second pair of adjacent OSLs, a second ground line interposed between the first pixel column and the first pair of adjacent OSLs, and a third ground line interposed between the second pair of adjacent OSLs and the second pixel column, the method comprising:
- applying an initial voltage to a first OSL of the first pair of adjacent OSLs during the row read operation;
- subsequent to applying the initial voltage, configuring a voltage of the first OSL of the first pair of adjacent OSLs to float;
- while the voltage of the first OSL of the first pair of adjacent OSLs floats, applying a signal transfer pulse to a first pixel of the first pixel column;
- receiving a pixel output signal of the first pixel of the first pixel column on a second OSL of the first pair of adjacent OSLs;
- and
- applying a low voltage signal to the first OSL of the first pair of adjacent OSLs during a pull-down time interval containing a falling edge of the signal transfer pulse.
An electronic device, comprising:
- a pixel array;
- and
- an electronic control system operably linked with the pixel array;
- wherein:
- the pixel array includes:
- a first pixel column and a second pixel column adjacent to the first pixel column;
- a set of associated electrical signal lines positioned with or between the first and second pixel columns, comprising:
- a first pair of adjacent output signal lines (OSLs);
- a second pair of adjacent OSLs interposed between the first pair of adjacent OSLs and the second pixel column;
- a first ground line interposed between the first pixel column and the first pair of adjacent OSLs;
- a second ground line interposed between the first pair of adjacent OSLs and the second pair of adjacent OSLs;
- and
- a third ground line interposed between the second pair of adjacent OSLs and the second pixel column;
- and
- the electronic control system is operable to apply a row read operation to the pixel array, the row read operation comprising:
- applying an initial voltage value to a first OSL of the first pair of adjacent OSLs;
- applying a signal transfer pulse to a pixel in the first pixel column;
- receiving on a second OSL of the first pair of adjacent OSLs a pixel output signal of the pixel in the first pixel column;
- and
- applying a low voltage pulse to the first OSL of the first pair of adjacent OSLs during a pull-down time interval containing a falling edge of the signal transfer pulse.
An image sensor comprising:
- a pixel array having a color filter array pattern, the pixel array comprising:
- a first column of pixels;
- a second column of pixels adjacent and parallel to the first column of pixels;
- and
- a set of associated electrical signal lines positioned with or between the first column of pixels and the second column of pixels and extending parallel to the first column of pixels, the set of associated electrical signal lines comprising:
- four pairs of adjacent output signal lines (OSLs);
- a first ground line interposed between the first column of pixels and a first pair of adjacent OSLs;
- a second ground line interposed between the first pair of adjacent OSLs and a second pair of adjacent OSLs;
- a third ground line interposed between the second pair of adjacent OSLs and a third pair of adjacent OSLs;
- a fourth ground line interposed between the third pair of adjacent OSLs and a fourth pair of adjacent OSLs;
- and
- a fifth ground line interposed between the fourth pair of adjacent OSLs and the second column of pixels;
- and
- an electronic control system linked with the set of associated electrical signal lines of the pixel array and configured to selectively float or bias a first OSL in a pair of adjacent OSLs while receiving a pixel output signal of a pixel in the first column of pixels on a second OSL in the pair of adjacent OSLs.
Dependencies are inferred from the claim text.