Digital clock and data recovery circuit and feedback loop circuit including the same

A feedback loop circuit comprising:

• a CTLE&VGA (continuous time linear equalizer & variable gain amplifier) circuit configured to receive an input signal from an outside and to amplify a magnitude of a signal corresponding to a frequency greater than or equal to a threshold;
• an analog-to-digital converter configured to receive the amplified signal and to quantize the amplified signal to convert the quantized amplified signal into a digital signal;
• a deserializer circuit configured to receive the converted digital signal and to parallelize the converted digital signal;
• a digital CDR (clock and data recovery) circuit configured to receive the parallelized digital signal and to generate a control code for controlling a sampling time of the input signal based on the parallelized digital signal;
• a PLL (phase-locked loop) circuit configured to receive a clock signal from an oscillator, to adjust a frequency of the clock signal, and to output an output clock signal of which a frequency is controlled;
• and
• a PS (phase shifter) circuit configured to receive the control code and the output clock signal, and to control a phase of the output clock signal based on the control code,
• wherein the PS circuit transfers the output clock signal of which the frequency is controlled to the analog-to-digital converter,
• wherein the analog-to-digital converter performs sampling on the input signal based on the output clock signal of which the frequency is controlled, and
• wherein the digital CDR circuit includes:
• a phase detector configured to receive the parallelized digital signal and to output a phase detection result signal corresponding to a determination result for a sampling time based on the parallelized digital signal;
• a charge pump configured to receive the phase detection result signal and to output an amplified signal obtained by multiplying the phase detection result signal by a gain;
• a loop filter configured to receive the amplified signal and to filter the amplified signal to output a filtered signal;
• and
• a phase shift control code generator configured to generate a control signal for controlling a phase of the output clock signal based on the filtered signal,
• wherein the parallelized digital signal includes a plurality of data signals and a plurality of error signals.