Network processor with command-template packet modification engine

Network packet processing circuitry, comprising at least one integrated circuit configured to:

• obtain an instance of a stream of packets;
• obtain an instance of a packet modification template, the packet modification template providing at least one command to insert content within the packets and change the stream of packets according to an output format of a network protocol;
• receive parameters, the parameters to modify the packet modification template, wherein the parameters are received from a same arithmetic logic unit (ALU) that determines the at least one command to modify the stream of packets;
• and
• apply the packet modification template to modify the stream of packets, wherein application of the packet modification template is performed using a plurality of processing components that are connected to the same ALU and arranged in parallel groups of serial pipelines, each of the serial pipelines applying a portion of the packet modification template within at least a first stage and a second stage in each of the serial pipelines.

At least one non-transitory machine-readable storage medium comprising instructions stored thereupon, which when executed by network packet processing circuitry, configure the network packet processing circuitry:

• receive a stream of packets;
• access a packet modification template, the packet modification template providing at least one command to insert content within the packets and change the stream of packets according to an output format of a network protocol;
• receive parameters, the parameters to modify the packet modification template, wherein the parameters are received from a same arithmetic logic unit (ALU) that determines the at least one command to modify the stream of packets;
• and
• apply the packet modification template to modify the stream of packets, wherein application of the packet modification template is performed using a plurality of processing components that are connected to the same ALU and arranged in parallel groups of serial pipelines, each of the serial pipelines applying a portion of the packet modification template within at least a first stage and a second stage in each of the serial pipelines.