Switch for transmitting packet, network on chip having the same, and operating method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsSeongmin Jo, Heeseong Lee, Jaehyun Kim, Jinsu Jung
Life of this patent
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Abstract
A Network-on-Chip (NoC) includes a packet transmission switch, and a corresponding method of operating the NoC includes storing packets received from an input terminal in a buffer, storing buffer locations in which each of the packets is stored in an ordering queue of an output terminal, and sequentially outputting the packets from the output terminal according to the buffer locations.
Claims20
A method of operating a network on a chip, comprising:
- receiving a first packet with a first output interface direction through a first master interface terminal in response to a clock signal;
- receiving a second packet with a second output interface direction through a second master interface terminal in response to the clock signal;
- storing the first packet and the second packet with corresponding buffer index queues in a buffer memory;
- sequentially outputting at least one of the stored packets through a first slave interface terminal based on the buffer index queues in response to the clock signal when at least one of the first output interface direction or the second output interface direction indicates the first slave interface terminal;
- and
- sequentially outputting at least one of the stored packets through a second slave interface terminal based on the buffer index queues in response to the clock signal when at least one of the first output interface direction or the second output interface direction indicates the second slave interface terminal.
The method of clam 1, wherein one of the first slave interface terminal or the second interface terminal outputs one packet one cycle of the clock signal earlier than the other packet.
A method of operating a Network-on-Chip (NoC), comprising:
- receiving first consecutive packets in a first master interface terminal starting from a first cycle of a clock signal;
- receiving second consecutive packets in a second master interface terminal starting from the first cycle;
- outputting third consecutive packets from a first slave interface terminal starting from a next cycle following the first cycle;
- and
- outputting fourth consecutive packets from a second slave interface terminal starting from a cycle following the next cycle.
A system on a chip comprising:
- a plurality of master devices;
- a plurality of slave devices;
- and
- a network-on-chip configured to arbitrate packets between the plurality of master devices and the plurality of slave devices,
- wherein the network-on-chip receives first consecutive packets in a first master interface terminal starting from a first cycle of a clock signal;
- receives second consecutive packets in a second master interface terminal starting from the first cycle;
- outputs third consecutive packets from a first slave interface terminal starting from a next cycle following the first cycle;
- and outputs fourth consecutive packets from a second slave interface terminal starting from a cycle following the next cycle.
Dependencies are inferred from the claim text.