Provisioning memory resources on flexible hardware platforms
AssigneeArista Networks, Inc.
InventorsMaxime Daniel Lorrillere, Suhas Raghunath Joshi
Life of this patent
Estimating the term…
Abstract
A method of allocating programmable memory in a network device includes receiving a set of desired features for the network device, and determining a plurality of constraints associated with the set of desired features. The plurality of constraints are converted into a plurality of Boolean representations of the constraints, and a feasibility is evaluated for the desired features based on the plurality of constraints.
Claims19
A method of allocating programmable memory in a network device the method comprising:
- receiving a set of desired features for the network device, wherein the set of desired features is supported by a set of tables to be stored across a plurality of memory banks of the programmable memory;
- determining a plurality of constraints associated with the set of desired features and the programmable memory;
- converting the plurality of constraints into a plurality of Boolean representations of the constraints wherein the plurality of Boolean representations of the constraints comprises Boolean representations each representing a state of memory allocation of one or more memory banks in the plurality of memory banks to a corresponding table in the set of tables;
- using a Satisfiability Modulo Theories (SMT) solver to generate a result by evaluating a feasibility of allocating the programmable memory for the desired features based on the Boolean representations of the constraints, wherein the result generated using the SMT solver indicates whether or not a solution exists for allocating the programmable memory for the desired features given the plurality of constraints;
- and
- returning the result.
A non-transitory computer readable medium comprising computer readable program code, which when executed by a computer processor enables the computer processor to perform a method, the method comprising:
- receiving a set of desired features for a network device, wherein the set of desired features comprises a Layer 2 switching feature or a Layer 3 routing feature and wherein the given Layer 2 switching feature is supported by at least a Layer 2 address database to be stored across multiple memory groups of programmable memory of the network device;
- determining a plurality of constraints associated with the set of desired features, wherein the plurality of constraints comprises a number of banks to be used in each of the multiple memory groups for the Layer 2 address database and wherein the plurality of constraints comprises a scale requirement associated with a memory allocation in some of the multiple memory groups that is reserved for a scaling of the Layer 2 address database;
- and
- evaluating a feasibility of allocating the programmable memory for the desired features based on the plurality of constraints at least in part by evaluating a feasibility of allocating portions of the multiple memory groups to the Layer 2 address database based on the number of banks to be used in each of the multiple memory groups and based on the scale requirement.
A network device comprising:
- a processor and a memory, wherein the processor and memory are configured to:
- receive a set of desired features for the network device, wherein each feature in the set of desired features is supported by a data structure to be implemented on memory blocks of programmable memory;
- determine a plurality of constraints associated with the set of desired features, wherein the plurality of constraints comprises connectivity constraints for the data structures supporting the set of desired features and wherein the connectivity constraints for the data structures each indicate one or more connections to at least a subset of the memory blocks of the programmable memory;
- evaluate a feasibility of allocating the memory blocks of the programmable memory for the desired features based at least in part on the connectivity constraints;
- and
- issue a notification that allocating the memory blocks of the programmable memory for the desired features is infeasible, wherein the notification comprises a conflict in memory allocation between first and second features in the set of desired features that is identified by the feasibility evaluation.
Dependencies are inferred from the claim text.