10G rate OLT terminal transceiver integrated chip based on XGSPON with EML laser

A 10G rate OLT terminal transceiver integrated chip based on XGSPON with EML laser, comprising:

• a burst mode receiver RX, a continuous mode transmitter TX and a digital control unit DIGIITAL, and a power module POWER;
• wherein the burst mode receiver RX amplifies an electrical signal which is originated from an optical signal from each ONU client and processed through a burst mode receiver TIA, processes amplitude detection of the electrical signal, determines if the electrical signal has an amplitude meeting threshold requirements, and output a detection result to a host, and uses a fast recovery module to discharge charges in an AC coupling capacitor to achieve multi-packet transmission without mutual interference, thereby meeting a XGSPON protocol;
• the continuous mode transmitter TX receives the electrical signal attenuated by a PCB board, and in response to a degree of attenuation, selects a bypass path BYPASS for transmission or outputs the electrical signal after a signal quality of the electrical signal is processed and improved by a clock data recovery path CDR to drive the EML laser;
• the digital control unit DIGIITAL communicates with the host, and provides control signals to the burst mode receiver RX and the continuous mode transmitter TX;
• and
• the power module POWER is arranged to provide power supply to the chip;
• the burst mode receiver RX comprises pre-amplifier Pre_Amplifier, a level detector Level Dectector, a 10G burst-mode limiting amplifier BurstLA_10G, a current mode logic output buffer CML BUFFER, a signal detection output buffer BUFFER and a fast recovery module;
• a non-inverting input and an inverting input of the pre-amplifier Pre_Amplifier are arranged to receive a burst data packet (the electrical signal) from the burst transimpedance amplifier TIA;
• the fast very module is arranged to provide a fast recovery circuit to ensure a timing sequence is correct, so that physical collision of two adjacently time sequenced burst packets is avoided;
• an output terminal of the pre-amplifier Pre_Amplifier is simultaneously connected to an input terminal of the 10G burst-mode limiting amplifier BurstLA_10G and an input terminal of the level detector LEVEL DETECTOR;
• an output terminal of the 10G burst-mode limiting amplifier BurstLA_10G Is connected to an input terminal of the current mode logic buffer CML BUFFER;
• an output terminal of the level detector LEVEL DETECTOR is simultaneously connected to input terminal of the signal detection output buffer BUFFER and an on/off control terminal of the current mode logic output buffer CML BUFFER;
• two output terminals of the current mode logic output buffer CML Buffer are connected to output pins RX_OUTP and RX_OUTN of the burst mode receiver RX respectively;
• an output terminal of the signal detection output buffer BUFFER is connected to a chip pin RX_SD, and the burst mode receiver RX sends a detection result to the host through the chip pin RX_SD;
• wherein in response to a reset signal sent from the host and received by a chip pin LA_RESET, the chip sends a feedback signal to the host through the pin RX_SD;
• the fast recovery module is built-in or external to the burst mode receiver RX, and the fast recovery module comprises resistors R7, R8, R9, R10, and switches S1 and S2,
• when the fast recovery module is external to the burst mode receiver RX, a non-inverting output terminal of the burst transimpedance amplifier TIA is connected to one end of the resistor R10 of the fast recover module, one end of the resistor R8 of the fast recovery module and a non-inverting input pin RX_INP of the chip through an AC coupling capacitor C9;
• an inverting output terminal of the burst transimpedance amplifier TIA is connected to one end of the resistor R9 and one end of the resistor R7 of the fast recovery module, and an inverting input pin RX_INN of the chip through the AC coupling capacitor C8;
• a non-inverting input pin RX_INP of the chip and an inverting input pin RX_INN of the chip are connected to a non-inverting input terminal and an inverting input terminal of the pre-amplifier Pre_Amplifier respectively;
• another end of the resistor R10 is connected to one end of the switch S1;
• another end of the resistor R9 is connected to one end of the switch S2;
• control ends of the switches S1 and S2 are connected to a reset signal line LA_RESET simultaneously;
• and
• a reference voltage pin Vref of the burst mode receiver RX is simultaneously connected to another end of the resistor R7, another end of the R8, another end of the switch S1 and another end of the switch S2,
• when the fast recovery module is built in the burst mode receiver RX, a non-inverting output terminal and an inverting output terminal of the burst transimpedance amplifier TIA are connected to a non-inventing input pin RX_INP of the chip and an inverting input pin RX_INN of the chip through AC coupling capacitors C9 and C8,
• inside the chip, the non-inverting input pin RX_INP of the chip is connected to one end of the resistor R10, one end of the resistor R8 and a non-inverting input terminal of the pre-amplifier Pre_Amplifier;
• the inventing input pin RX_INN of the chip is connected to one end of the resistor R9, one end of the resistor R7 and an inverting input of the pre-amplifier Pre_Amplifier;
• another end of the resistor R10 is connected to one end of the switch S1;
• another end of the resistor R9 is connected to one end of the switch S2;
• control ends of the switches S1 and S2 are connected to a reset signal line LA_RESET of the chip simultaneously, and
• a reference voltage Vref of the burst mode receiver RX is simultaneously connected to another end of the resistor R7, another end of the R8, another end of the switch S1 and another end of the switch S2.