Capacitor digital-to-analog converter using random reset signal and integrated circuit including the same

An integrated circuit comprising:

• an internal circuit;
• and
• a capacitor digital-to-analog converter (CDAC) configured to perform a digital-to-analog conversion on at least one of an input and an output of the internal circuit, and
• wherein the capacitor digital-to-analog converter includes:
• a clock generator configured to generate an internal clock signal and a reset control signal based on an external clock signal, the internal clock signal being regularly toggled, the reset control signal being regularly toggled;
• a random reset control signal generator configured to generate a random reset control signal based on the reset control signal, the random reset control signal being irregularly toggled;
• a first capacitor array including a plurality of capacitors, and configured to generate a first summation voltage based on a first reference voltage and a second reference voltage, the plurality of capacitors in the first capacitor array being connected to a first summation node and having different capacitances, the first summation voltage corresponding to a first input digital signal;
• a first reset circuit configured to initialize the first summation node based on the random reset control signal and a change in the first input digital signal;
• and
• an output buffer configured to generate a first analog output voltage by buffering the first summation voltage,
• wherein the capacitor digital-to-analog converter is configured to operate in a reset phase for initializing the first summation node, and during the reset phase, a value of the first input digital signal sequentially increases based on the internal clock signal.

A capacitor digital-to-analog converter (CDAC) comprising:

• a clock generator configured to generate an internal clock signal and a reset control signal based on an external clock signal, the internal clock signal being regularly toggled during a reset phase and a conversion phase, the reset control signal being regularly toggled during the reset phase and having a deactivation state during the conversion phase;
• a random reset control signal generator configured to generate a random reset control signal based on the internal clock signal and the reset control signal, the random reset control signal being irregularly toggled during the reset phase and having the deactivation state during the conversion phase;
• a capacitor array configured to generate a summation voltage corresponding to an input digital signal based on a reference voltage and a ground voltage, the capacitor array including:
• first to N-th capacitors connected to a summation node and having different capacitances, where N is a natural number greater than or equal to two;
• and
• first to N-th switches connected to the first to N-th capacitors;
• a reference voltage generator configured to generate the reference voltage, and including a decoupling capacitor;
• a decoder logic circuit configured to generate the input digital signal based on the internal clock signal;
• a reset circuit configured to initialize the summation node based on a reset voltage, the random reset control signal and a change in the input digital signal during the reset phase;
• and
• an output buffer configured to generate an analog output voltage by buffering the summation voltage,
• wherein, during the reset phase, a value of the input digital signal sequentially increases based on the internal clock signal, a voltage level of the summation voltage is initialized to a voltage level of the reset voltage in response to the random reset control signal having an activation state, and the voltage level of the summation voltage sequentially increases based on the input digital signal in response to the random reset control signal having the deactivation state, and
• wherein, during the conversion phase, the input digital signal has a target value for a digital-to-analog conversion, and the summation voltage has a target voltage level corresponding to the target value.