Single-ended to differential-ended converter circuit, successive-approximation register analog-to-digital converter utilizing same, and method of converting single-ended signal to differential-ended signal

A successive-approximation register (SAR) analog-to-digital converter (ADC), comprising:

• a comparator having a first input terminal and a second input terminal and configured to generate a comparison result;
• a SAR coupled to the comparator and configured to store the comparison result;
• a first sampling capacitor having a first end and a second end, the first end being coupled to the first input terminal, and the second end receiving a reference voltage;
• a second sampling capacitor having a third end and a fourth end, the third end being coupled to the second input terminal;
• a first capacitor group comprising a plurality of first capacitors, an end of the first capacitors being coupled to the first input terminal;
• a first switch group coupled to another end of the first capacitors;
• a second capacitor group comprising a plurality of second capacitors, an end of the second capacitors being coupled to the second input terminal;
• a second switch group coupled to another end of the second capacitors;
• a control circuit coupled to the SAR and configured to control the first switch group and the second switch group according to the comparison result;
• and
• a third switch group coupled to the first input terminal, the second input terminal, and the fourth end;
• wherein at a first time point, the third switch group couples the first input terminal and the first end to a single-ended signal, couples the second input terminal and the third end to the reference voltage or a middle voltage value of a swing of the single-ended signal, and couples the fourth end to the single-ended signal;
• wherein the third switch group couples the fourth end to the reference voltage at a second time point which is later than the first time point.

A method of converting a single-ended signal to a differential signal, comprising:

• providing a first sampling capacitor which has a first end and a second end;
• providing a second sampling capacitor which has a third end and a fourth end;
• at a first time point, controlling the first end to receive the single-ended signal, controlling the second end to receive a reference voltage, controlling the third end to receive the reference voltage or a middle voltage value of a swing of the single-ended signal, and controlling the fourth end to receive the single-ended signal;
• and
• at a second time point, controlling the second end to receive the reference voltage and controlling the fourth end to receive the reference voltage;
• wherein the first end and the third end output the differential signal after the second time point which is later than the first time point;
• wherein the first time point corresponds to one of a rising edge and a falling edge of a clock, and the second time point corresponds to another of the rising edge and the falling edge of the clock.