Analog-to-digital conversion circuit and method having remained time measuring mechanism

An analog-to-digital conversion circuit having remained time measuring mechanism, comprising:

• a digital-to-analog conversion circuit configured to sample a positive terminal input voltage and a negative terminal input voltage when a sampling indication signal is at a sampling state and output a positive terminal output voltage and a negative terminal output voltage when the sampling indication signal is at a sampling finished state;
• a comparator configured to, in each of a plurality of comparison stages, compare the positive terminal output voltage and the negative terminal output voltage to generate a comparison result, wherein a number of the comparison stages is a default number;
• a control circuit configured to, in each of the comparison stages, switch a configuration of the digital-to-analog conversion circuit by using a set of digital codes according to the comparison result, and configured to output the corresponding set of digital codes as a digital output signal when a conversion finished criteria is satisfied;
• a comparison determining circuit configured to, in each of the comparison stages, set a stage indication signal to be a comparison stage unfinished state before the comparison result is generated and set the stage indication signal to be a comparison stage finished state after the comparison result is generated;
• a comparison stage counting circuit configured to, in each of the comparison stages, accumulate a number of times that the comparison is finished when the stage indication signal is at the comparison stage finished state, set a conversion indication signal to be a conversion unfinished state before the number of the number of times that the comparison is finished reaches the default number and set the conversion indication signal to be the conversion finished state when the number of times that the comparison is finished reaches the default number;
• and
• a time accumulating circuit configured to start to accumulate a remained time when the conversion indication signal is at the conversion finished state and finish accumulation when the sampling indication signal is at the sampling state next time.