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US 12,113,539 B1Granted
Field programmable gate array with external phase-locked loop
AssigneeHFT Solutions, LLC
InventorNima Badizadegan
Life of this patent
Estimating the term…
Abstract
The present invention relates to a field programmable gate array system that provides phase control with minimal latency.
Claims36
A method for processing a first serial data stream comprising market data, using a field programmable gate array system, to generate a second serial data stream, wherein the method comprises the steps of:
- (a) receiving, by a field programmable array, a clock signal;
- (b) receiving, by a deserializer in the field programmable gate array, the first serial data stream;
- (c) generating a receiver side clock signal;
- (d) converting, by the deserializer, the first serial data stream into a first plurality of parallel data streams;
- (e) transmitting, from the deserializer to computational circuitry in the field programmable gate array, the first plurality of parallel data streams;
- (f) transmitting, from the field programmable gate array to a phase lock loop of the field programmable gate array system that is not within the field programmable gate array, the receiver side clock signal;
- (g) performing, by the computational circuitry, a set of operations on at least a portion of the first plurality of parallel data streams using the receiver side clock signal to generate a second plurality of parallel data streams;
- (h) generating, using the phase lock loop, a second clock signal;
- (i) generating a transmitter side clock signal derived from the second clock signal;
- and
- (j) transmitting, from the field programmable gate array system, the second serial data stream, derived from the second plurality of parallel data streams and the transmitter side clock signal,
- wherein steps (a)-(j) are performed without use of clock domain crossing operations.
9 more elements
A method for processing a first serial data stream comprising market data, using a field programmable gate array system, to generate a second serial data stream, wherein the method comprises the steps of:
- (a) receiving, by a field programmable array, a clock signal;
- (b) receiving, by a deserializer in the field programmable gate array, the first serial data stream;
- (c) generating a receiver side clock signal;
- (d) converting, by the deserializer, the first serial data stream into a first plurality of parallel data streams;
- (e) transmitting, from the deserializer to computational circuitry in the field programmable gate array, the first plurality of parallel data streams;
- (f) transmitting, from the field programmable gate array to a phase lock loop of the field programmable gate array system that is not within the field programmable gate array, the receiver side clock signal;
- (g) performing, by the computational circuitry, a set of operations on at least a portion of the first plurality of parallel data streams using the receiver side clock signal to generate a second plurality of parallel data streams;
- (h) generating, using the phase lock loop, a second clock signal;
- (i) generating a transmitter side clock signal derived from the second clock signal;
- and
- (j) transmitting, from the field programmable gate array system, the second serial data stream, derived from the second plurality of parallel data streams and the transmitter side clock signal,
- wherein steps (a)-(j) are performed without use of clock domain crossing circuits.
9 more elements
A method for processing a first serial data stream comprising market data, using a field programmable gate array system, to generate a second serial data stream, wherein the method comprises the steps of:
- (a) receiving, by a field programmable array, a clock signal;
- (b) receiving, by a deserializer in the field programmable gate array, the first serial data stream;
- (c) generating a receiver side clock signal;
- (d) converting, by the deserializer, the first serial data stream into a first plurality of parallel data streams;
- (e) transmitting, from the deserializer to computational circuitry in the field programmable gate array, the first plurality of parallel data streams;
- (f) transmitting, from the field programmable gate array to a phase lock loop of the field programmable gate array system that is not within the field programmable gate array, the receiver side clock signal;
- (g) performing, by the computational circuitry, a set of operations on at least a portion of the first plurality of parallel data streams using the receiver side clock signal to generate a second plurality of parallel data streams;
- (h) generating, using the phase lock loop, a second clock signal;
- (i) generating a transmitter side clock signal derived from the second clock signal;
- and
- (j) transmitting, from the field programmable gate array system, the second serial data stream, derived from the second plurality of parallel data streams and the transmitter side clock signal,
- wherein the field programmable gate array system includes clock domain crossing circuitry and steps (a)-(j) are performed without use of the clock domain crossing circuitry.
9 more elements
A method for processing a first serial data stream comprising market data, using a field programmable gate array system, to generate a second serial data stream, wherein the method comprises the steps of:
- (a) receiving, by a field programmable array, a clock signal;
- (b) receiving, by a deserializer in the field programmable gate array, the first serial data stream;
- (c) generating a receiver side clock signal;
- (d) converting, by the deserializer, the first serial data stream into a first plurality of parallel data streams;
- (e) transmitting, from the deserializer to computational circuitry in the field programmable gate array, the first plurality of parallel data streams;
- (f) transmitting, from the field programmable gate array to a phase lock loop of the field programmable gate array system that is not within the field programmable gate array, the receiver side clock signal;
- (g) performing, by the computational circuitry, a set of operations on at least a portion of the first plurality of parallel data streams using the receiver side clock signal to generate a second plurality of parallel data streams;
- (h) generating, using the phase lock loop, a second clock signal;
- (i) generating a transmitter side clock signal derived from the second clock signal;
- and
- (j) transmitting, from the field programmable gate array system, the second serial data stream, derived from the second plurality of parallel data streams and the transmitter side clock signal,
- wherein a maximum delay associated with transferring data between a receiver side clock domain associated with the receiver side clock signal and a transmitter side clock domain associated with the transmitter side clock signal is less than 1 clock cycle.
9 more elements
A method for processing a first serial data stream comprising market data, using a field programmable gate array system, to generate a second serial data stream, wherein the method comprises the steps of:
- (a) receiving, by a field programmable array, a clock signal;
- (b) receiving, by a deserializer in the field programmable gate array, the first serial data stream;
- (c) generating a receiver side clock signal;
- (d) converting, by the deserializer, the first serial data stream into a first plurality of parallel data streams;
- (e) transmitting, from the deserializer to computational circuitry in the field programmable gate array, the first plurality of parallel data streams;
- (f) transmitting, from the field programmable gate array to a phase lock loop of the field programmable gate array system that is not within the field programmable gate array, the receiver side clock signal;
- (g) performing, by the computational circuitry, a set of operations on at least a portion of the first plurality of parallel data streams using the transmitter side clock signal to generate a second plurality of parallel data streams;
- (h) generating, using the phase lock loop, a second clock signal;
- (i) generating a transmitter side clock signal derived from the second clock signal;
- and
- (j) transmitting, from the field programmable gate array system, the second serial data stream, derived from the second plurality of parallel data streams and the transmitter side clock signal,
- wherein steps (a)-(j) are performed without clock domain crossing operations.
9 more elements
A method for processing a first serial data stream comprising market data, using a field programmable gate array system, to generate a second serial data stream, wherein the method comprises the steps of:
- (a) receiving, by a field programmable array, a clock signal;
- (b) receiving, by a deserializer in the field programmable gate array, the first serial data stream;
- (c) generating a receiver side clock signal;
- (d) converting, by the deserializer, the first serial data stream into a first plurality of parallel data streams;
- (e) transmitting, from the deserializer to computational circuitry in the field programmable gate array, the first plurality of parallel data streams;
- (f) transmitting, from the field programmable gate array to a phase lock loop of the field programmable gate array system that is not within the field programmable gate array, the receiver side clock signal;
- (g) performing, by the computational circuitry, a set of operations on at least a portion of the first plurality of parallel data streams using the transmitter side clock signal to generate a second plurality of parallel data streams;
- (h) generating, using the phase lock loop, a second clock signal;
- (i) generating a transmitter side clock signal derived from the second clock signal;
- and
- (j) transmitting, from the field programmable gate array system, the second serial data stream, derived from the second plurality of parallel data streams and the transmitter side clock signal,
- wherein steps (a)-(j) are performed without use of clock domain crossing circuits.
9 more elements
A method for processing a first serial data stream comprising market data, using a field programmable gate array system, to generate a second serial data stream, wherein the method comprises the steps of:
- (a) receiving, by a field programmable array, a clock signal;
- (b) receiving, by a deserializer in the field programmable gate array, the first serial data stream;
- (c) generating a receiver side clock signal;
- (d) converting, by the deserializer, the first serial data stream into a first plurality of parallel data streams;
- (e) transmitting, from the deserializer to computational circuitry in the field programmable gate array, the first plurality of parallel data streams;
- (f) transmitting, from the field programmable gate array to a phase lock loop of the field programmable gate array system that is not within the field programmable gate array, the receiver side clock signal;
- (g) performing, by the computational circuitry, a set of operations on at least a portion of the first plurality of parallel data streams using the transmitter side clock signal to generate a second plurality of parallel data streams;
- (h) generating, using the phase lock loop, a second clock signal;
- (i) generating a transmitter side clock signal derived from the second clock signal;
- and
- (j) transmitting, from the field programmable gate array system, the second serial data stream, derived from the second plurality of parallel data streams and the transmitter side clock signal,
- wherein the field programmable gate array system includes clock domain crossing circuitry and steps (a)-(j) are performed without use of clock domain crossing circuitry.
9 more elements
A method for processing a first serial data stream comprising market data, using a field programmable gate array system, to generate a second serial data stream, wherein the method comprises the steps of:
- (a) receiving, by a field programmable array, a clock signal;
- (b) receiving, by a deserializer in the field programmable gate array, the first serial data stream;
- (c) generating a receiver side clock signal;
- (d) converting, by the deserializer, the first serial data stream into a first plurality of parallel data streams;
- (e) transmitting, from the deserializer to computational circuitry in the field programmable gate array, the first plurality of parallel data streams;
- (f) transmitting, from the field programmable gate array to a phase lock loop of the field programmable gate array system that is not within the field programmable gate array, the receiver side clock signal;
- (g) performing, by the computational circuitry, a set of operations on at least a portion of the first plurality of parallel data streams using the transmitter side clock signal to generate a second plurality of parallel data streams;
- (h) generating, using the phase lock loop, a second clock signal;
- (i) generating a transmitter side clock signal derived from the second clock signal;
- and
- (j) transmitting, from the field programmable gate array system, the second serial data stream, derived from the second plurality of parallel data streams and the transmitter side clock signal,
- wherein a maximum delay associated with transferring data between a receiver side clock domain associated with the receiver side clock signal and a transmitter side clock domain associated with the transmitter side clock signal is less than 1 clock cycle.
9 more elements
A method for processing a first serial data stream comprising market data, using a field programmable gate array system, to generate a second serial data stream, wherein the method comprises the steps of:
- (a) receiving, by a field programmable array, a clock signal;
- (b) receiving, by a deserializer in the field programmable gate array, the first serial data stream;
- (c) generating a receiver side clock signal;
- (d) converting, by the deserializer, the first serial data stream into a first plurality of parallel data streams;
- (e) transmitting, from the deserializer to computational circuitry in the field programmable gate array, the first plurality of parallel data streams;
- (f) transmitting, from the field programmable gate array to a phase lock loop of the field programmable gate array system that is not within the field programmable gate array, the receiver side clock signal;
- (g) performing, by the computational circuitry, a first set of operations on at least a portion of the first plurality of parallel data streams using the receiver side clock signal to generate a second plurality of parallel data streams;
- (h) generating, using the phase lock loop, a second clock signal;
- (i) generating a transmitter side clock signal derived from the second clock signal;
- and
- (j) transmitting, from the field programmable gate array system, the second serial data stream, derived from the second plurality of parallel data streams and the transmitter side clock signal,
- wherein steps (a)-(j) are performed without use of clock domain crossing operations.
9 more elements
A method for processing a first serial data stream comprising market data, using a field programmable gate array system, to generate a second serial data stream, wherein the method comprises the steps of:
- (a) receiving, by a field programmable array, a clock signal;
- (b) receiving, by a deserializer in the field programmable gate array, the first serial data stream;
- (c) generating a receiver side clock signal;
- (d) converting, by the deserializer, the first serial data stream into a first plurality of parallel data streams;
- (e) transmitting, from the deserializer to computational circuitry in the field programmable gate array, the first plurality of parallel data streams;
- (f) transmitting, from the field programmable gate array to a phase lock loop of the field programmable gate array system that is not within the field programmable gate array, the receiver side clock signal;
- (g) performing, by the computational circuitry, a first set of operations on at least a portion of the first plurality of parallel data streams using the receiver side clock signal to generate a second plurality of parallel data streams;
- (h) generating, using the phase lock loop, a second clock signal;
- (i) generating a transmitter side clock signal derived from the second clock signal;
- and
- (j) transmitting, from the field programmable gate array system, the second serial data stream, derived from the second plurality of parallel data streams and the transmitter side clock signal,
- wherein steps (a)-(j) are performed without use of clock domain crossing circuits.
9 more elements
A method for processing a first serial data stream comprising market data, using a field programmable gate array system, to generate a second serial data stream, wherein the method comprises the steps of:
- (a) receiving, by a field programmable array, a clock signal;
- (b) receiving, by a deserializer in the field programmable gate array, the first serial data stream;
- (c) generating a receiver side clock signal;
- (d) converting, by the deserializer, the first serial data stream into a first plurality of parallel data streams;
- (e) transmitting, from the deserializer to computational circuitry in the field programmable gate array, the first plurality of parallel data streams;
- (f) transmitting, from the field programmable gate array to a phase lock loop of the field programmable gate array system that is not within the field programmable gate array, the receiver side clock signal;
- (g) performing, by the computational circuitry, a first set of operations on at least a portion of the first plurality of parallel data streams using the receiver side clock signal to generate a second plurality of parallel data streams;
- (h) generating, using the phase lock loop, a second clock signal;
- (i) generating a transmitter side clock signal derived from the second clock signal;
- and
- (j) transmitting, from the field programmable gate array system, the second serial data stream, derived from the second plurality of parallel data streams and the transmitter side clock signal,
- wherein the field programmable gate array system includes clock domain crossing circuitry and steps (a)-(j) are performed without use of clock domain crossing circuitry.
9 more elements
A method for processing a first serial data stream comprising market data, using a field programmable gate array system, to generate a second serial data stream, wherein the method comprises the steps of:
- (a) receiving, by a field programmable array, a clock signal;
- (b) receiving, by a deserializer in the field programmable gate array, the first serial data stream;
- (c) generating a receiver side clock signal;
- (d) converting, by the deserializer, the first serial data stream into a first plurality of parallel data streams;
- (e) transmitting, from the deserializer to computational circuitry in the field programmable gate array, the first plurality of parallel data streams;
- (f) transmitting, from the field programmable gate array to a phase lock loop of the field programmable gate array system that is not within the field programmable gate array, the receiver side clock signal;
- (g) performing, by the computational circuitry, a first set of operations on at least a portion of the first plurality of parallel data streams using the receiver side clock signal to generate a second plurality of parallel data streams;
- (h) generating, using the phase lock loop, a second clock signal;
- (i) generating a transmitter side clock signal derived from the second clock signal;
- and
- (j) transmitting, from the field programmable gate array system, the second serial data stream, derived from the second plurality of parallel data streams and the transmitter side clock signal,
- wherein a maximum delay associated with transferring data between a receiver side clock domain associated with the receiver side clock signal and a transmitter side clock domain associated with the transmitter side clock signal is less than 1 clock cycle.
9 more elements
Dependencies are inferred from the claim text.