US 12,113,481 B2Granted

Switch circuit, mixer, and electronic device

AssigneeHuawei Technologies Co., Ltd.

InventorsYongli Zhou, Xiangju Jin, Yan Lai

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Abstract

A switch circuit, a mixer, and an electronic device, where the switch circuit includes a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor, both a gate of the first MOS transistor and a gate of the fourth MOS transistor are connected to a first port, and both a gate of the second MOS transistor and a gate of the third MOS transistor are connected to a second port; and a lead between the gate of the first MOS transistor and the first port, a lead between the gate of the second MOS transistor and the second port, a lead between the gate of the third MOS transistor and the second port, and a lead between the gate of the fourth MOS transistor and the first port all have an equal length. In this way, linearity is relatively high.

Claims20

Dependent claims

A switch circuit, comprising:

multiple transistors including a first metal-oxide-semiconductor (MOS) transistor having a first gate, a second MOS transistor having a second gate, a third MOS transistor having a third gate, and a fourth MOS transistor having a fourth gate, wherein the first MOS transistor and the third MOS transistor are symmetrically aligned along a first symmetry axis, wherein the second MOS transistor and the fourth MOS transistor are symmetrically aligned along the first symmetry axis, wherein the first MOS transistor and the second MOS transistor are symmetrically aligned forward and backward along a second symmetry axis, wherein the third MOS transistor and the fourth MOS transistor are symmetrically aligned forward and backward along the second symmetry axis, and wherein the first symmetry axis and the second symmetry axis are perpendicular to each other;
a first port connected to both the first gate and the fourth gate;
a second port connected to the second gate and the third gate;
a first lead between the first gate and the first port;
a second lead between the second gate and the second port;
a third lead between the third gate and the second port;
a fourth lead between the fourth gate and the first port, wherein the first lead, the second lead, the third lead, and the fourth lead all have an equal length;
a first direct lead between the first gate and the fourth gate passing through a first position;
a second direct lead between the second gate and the third gate passing through a second position, wherein the first position and the second position are same positions at different layers in the switch circuit, and wherein leads from the first gate to the first position, from the second gate to the second position, from the third gate to the second position, and from the fourth gate to the first position have an equal length;
a fifth lead comprising:
a first end connected to a third position of the first direct lead;
a second end connected to the first port;
a first part located on a first side of the first symmetry axis;
and
a second part located on a second side of the first symmetry axis, wherein the first side is opposite the second side of the first symmetry axis, and wherein the fifth lead passes through a fifth position,
a sixth lead comprising:
a third end connected to a fourth position of the second direct lead;
a fourth end connected to the second port, wherein the third position and the fourth position are symmetrical along the first symmetry axis, and wherein the switch circuit is symmetrical along the first symmetry axis;
a third part located on the first side of the first symmetry axis;
and
a fourth part located on the second side of the first symmetry axis, wherein the sixth lead passes through a sixth position, and wherein the fifth position and the sixth position are same positions at different layers in the switch circuit.

18 more elements

A mixer, comprising:

a switch circuit including:
multiple transistors including a first metal-oxide-semiconductor (MOS) transistor having a first gate, a second MOS transistor having a second gate, a third MOS transistor having a third gate, and a fourth MOS transistor having a fourth gate, wherein the first MOS transistor and the third MOS transistor are symmetrically aligned along a first symmetry axis, wherein the second MOS transistor and the fourth MOS transistor are symmetrically aligned along the first symmetry axis, wherein the first MOS transistor and the second MOS transistor are symmetrically aligned forward and backward along a second symmetry axis, wherein the third MOS transistor and the fourth MOS transistor are symmetrically aligned forward and backward along the second symmetry axis, and wherein the first symmetry axis and the second symmetry axis are perpendicular to each other;
a first port connected to both the first gate and the fourth gate;
a second port connected to the second gate and the third gate;
a first lead between the first gate of the first MOS transistor and the first port;
a second lead between the second gate of the second MOS transistor and the second port;
a third lead between the third gate of the third MOS transistor and the second port;
a fourth lead between the fourth gate of the fourth MOS transistor and the first port,
wherein the first lead, the second lead, the third lead, and the fourth lead all have an equal length;
a first direct lead between the first gate and the fourth gate passing through a first position;
a second direct lead between the second gate and the third gate passing through a second position, wherein the first position and the second position are same positions at different layers in the switch circuit, and wherein leads from the first gate to the first position, from the second gate to the second position, from the third gate to the second position, and from the fourth gate to the first position have an equal length;
a fifth lead comprising:
a first end connected to a third position of the first direct lead;
a second end connected to the first port;
a first part located on a first side of the first symmetry axis;
and
a second part located on a second side of the first symmetry axis, wherein the first side is opposite the second side of the first symmetry axis, and wherein the fifth lead passes through a fifth position,
a sixth lead comprising:
a third end connected to a fourth position of the second direct lead;
a fourth end connected to the second port, wherein the third position and the fourth position are symmetrical along the first symmetry axis, and wherein the switch circuit is symmetrical along the first symmetry axis;
a third part located on the first side of the first symmetry axis;
and
a fourth part located on the second side of the first symmetry axis, wherein the sixth lead passes through a sixth position, and wherein the fifth position and the sixth position are same positions at different layers in the switch circuit.

20 more elements

A mixer, comprising:

a first metal-oxide-semiconductor (MOS) transistor group including a circuit structure, a first MOS transistor having a first gate, a second MOS transistor having a second gate, a third MOS transistor having a third gate, and a fourth MOS transistor having a fourth gate, wherein the first MOS transistor and the third MOS transistor are symmetrically aligned along a first symmetry axis, wherein the second MOS transistor and the fourth MOS transistor are symmetrically aligned along the first symmetry axis, wherein the first MOS transistor and the second MOS transistor are symmetrically aligned forward and backward along a second symmetry axis, wherein the third MOS transistor and the fourth MOS transistor are symmetrically aligned forward and backward along the second symmetry axis, and wherein the first symmetry axis and the second symmetry axis are perpendicular to each other;
a second MOS transistor group including a same circuit structure as the circuit structure of the first MOS transistor group, wherein the first MOS transistor group and the second MOS transistor group are symmetrically aligned along a reference symmetry axis;
a first local oscillator port connected to the first gate and the fourth gate;
a second local oscillator port connected to the second gate and the third gate;
and
a first lead between the first gate and the first local oscillator port;
a second lead between the second gate and the second local oscillator port;
a third lead between the third gate and the second local oscillator port;
and
a fourth lead between the fourth gate and the first local oscillator port,
wherein the first lead, the second lead, the third lead, and the fourth lead all have an equal length;
a first direct lead between the first gate and the fourth gate passing through a first position;
a second direct lead between the second gate and the third gate passing through a second position, wherein the first position and the second position are same positions at different layers in the mixer, and wherein leads from the first gate to the first position, from the second gate to the second position, from the third gate to the second position, and from the fourth gate to the first position have an equal length;
a fifth lead comprising:
a first end connected to a third position of the first direct lead;
a second end connected to the first local oscillator port;
a first part located on a first side of the first symmetry axis;
and
a second part located on a second side of the first symmetry axis, wherein the first side is opposite the second side of the first symmetry axis, and wherein the fifth lead passes through a fifth position,
a sixth lead comprising:
a third end connected to a fourth position of the second direct lead;
a fourth end connected to the second local oscillator port, wherein the third position and the fourth position are symmetrical along the first symmetry axis, and wherein the mixer is symmetrical along the first symmetry axis;
a third part located on the first side of the first symmetry axis;
and
a fourth part located on the second side of the first symmetry axis, wherein the sixth lead passes through a sixth position, and wherein the fifth position and the sixth position are same positions at different layers in the mixer.

22 more elements

An electronic device, comprising:

a mixer including:
a first metal-oxide-semiconductor (MOS) transistor group including a circuit structure, a first MOS transistor having a first gate, a second MOS transistor having a second gate, a third MOS transistor having a third gate, and a fourth MOS transistor having a fourth gate, wherein the first MOS transistor and the third MOS transistor are symmetrically aligned along a first symmetry axis, wherein the second MOS transistor and the fourth MOS transistor are symmetrically aligned along the first symmetry axis, wherein the first MOS transistor and the second MOS transistor are symmetrically aligned forward and backward along a second symmetry axis, wherein the third MOS transistor and the fourth MOS transistor are symmetrically aligned forward and backward along the second symmetry axis, and wherein the first symmetry axis and the second symmetry axis are perpendicular to each other;
a second MOS transistor group including a same circuit structure as the circuit structure of the first MOS transistor group, wherein the first MOS transistor group and the second MOS transistor group are symmetrically aligned along a reference symmetry axis;
a first local oscillator port connected to both the first gate and the fourth gate;
a second local oscillator port connected to both the second gate and the third gate;
a first lead between the first gate and the first local oscillator port;
a second lead between the second gate and the second local oscillator port;
a third lead between the third gate and the second local oscillator port;
a fourth lead between the fourth gate and the first local oscillator port,
wherein the first lead, the second lead, the third lead, and the fourth lead all have an equal length;
a first direct lead between the first gate and the fourth gate passing through a first position;
a second direct lead between the second gate and the third gate passing through a second position, wherein the first position and the second position are same positions at different layers in the mixer, and wherein leads from the first gate to the first position, from the second gate to the second position, from the third gate to the second position, and from the fourth gate to the first position have an equal length;
a fifth lead comprising:
a first end connected to a third position of the first direct lead;
a second end connected to the first local oscillator port;
a first part located on a first side of the first symmetry axis;
and
a second part located on a second side of the first symmetry axis, wherein the first side is opposite the second side of the first symmetry axis, and wherein the fifth lead passes through a fifth position,
a sixth lead comprising:
a third end connected to a fourth position of the second direct lead;
a fourth end connected to the second local oscillator port, wherein the third position and the fourth position are symmetrical along the first symmetry axis, and wherein the mixer is symmetrical along the first symmetry axis;
a third part located on the first side of the first symmetry axis;
and
a fourth part located on the second side of the first symmetry axis, wherein the sixth lead passes through a sixth position, and wherein the fifth position and the sixth position are same positions at different layers in the mixer.

21 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/514,564Filed 29 Oct 2021 · continuation
Priority: 30 Apr 2019
Published: US 2022/0052645 A117 Feb 2022
Granted: 8 Oct 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H03D 7/1441
With transistors: using field-effect transistors
H03D 7/1458
With transistors: double balanced arrangements, i.e. where both input signals are differential
H03D 7/1466
With transistors: passive mixer arrangements
H03D 7/1491
With transistors: arrangements to linearise a transconductance stage of a mixer arrangement

Family

PCT/CN2019/085335Parent of this continuation · filed 30 Apr 2019
US 2022/0052645 A1Pre-grant publication · published 17 Feb 2022
US 12,113,481 B2This patent

From the US filing history. Foreign family members aren’t listed.

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