Metal oxide transistor, display panel and display apparatus

A display panel, comprising:

• a substrate;
• and
• a plurality of pixel circuits located at a side of the substrate, wherein each of the plurality of pixel circuits comprises a metal oxide transistor comprising a first gate electrode, an active layer, a second gate electrode, and a source-drain electrode that are stacked,
• wherein the source-drain electrode comprises a source electrode and a drain electrode;
• wherein the active layer comprises a plurality of active sub-layers, and wherein each of the plurality of active sub-layers comprises a metal oxide and defines a semiconductor zone;
• wherein the plurality of active sub-layers comprises a first active sub-layer, a second active sub-layer, and a third active sub-layer, the first active sub-layer being located between the second active sub-layer and the first gate electrode, and the third active sub-layer being located between the second active sub-layer and the second gate electrode;
• and
• wherein a semiconductor zone of the first active sub-layer has an oxygen ion doping concentration CO_1, a semiconductor zone of the second active sub-layer has an oxygen ion doping concentration CO_2, and a semiconductor zone of the third active sub-layer has an oxygen ion doping concentration CO_3, where CO_1<CO_2, and CO_3<CO_2.

A display apparatus comprising a display panel, wherein the display panel comprises a substrate and a plurality of pixel circuits located at a side of the substrate,

• wherein each of the plurality of pixel circuits comprises a metal oxide transistor comprising a first gate electrode, an active layer, a second gate electrode, and a source-drain electrode that are stacked,
• wherein the source-drain electrode comprises a source electrode and a drain electrode;
• wherein the active layer comprises a plurality of active sub-layers, wherein each of the plurality of active sub-layers comprises a metal oxide and defines a semiconductor zone;
• wherein the plurality of active sub-layers comprises a first active sub-layer, a second active sub-layer, and a third active sub-layer, the first active sub-layer being located between the second active sub-layer and the first gate electrode, and the third active sub-layer being located between the second active sub-layer and the second gate electrode;
• and
• wherein a semiconductor zone of the first active sub-layer has an oxygen ion doping concentration CO_1, a semiconductor zone of the second active sub-layer has an oxygen ion doping concentration CO_2, and a semiconductor zone of the third active sub-layer has an oxygen ion doping concentration CO_3, where CO_1<CO_2, and CO_3<CO_2.