Strain enhanced SiC power semiconductor device and method of manufacturing
AssigneeHitachi Energy Ltd
InventorsStephan Wirths, Lars Knoll
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AssigneeHitachi Energy Ltd
InventorsStephan Wirths, Lars Knoll
Estimating the term…
A SiC transistor device includes a SiC semiconductor substrate, a SiC epitaxial layer formed on the top surface of the SiC semiconductor substrate, a source structure formed in the top surface of the SiC epitaxial layer, a source contact structure electrically coupled to the top surface of the source structure, and a gate structure that includes a gate dielectric, a metal gate, and a gate insulation. A first backside metal contact is formed on the bottom surface of the SiC semiconductor substrate, a stress inducing layer is formed on the first backside metal contact, and a second backside metal contact is formed on the stress inducing layer.
A SiC transistor device comprising:
A method of manufacturing a SiC transistor device comprising:
A method of manufacturing a SiC transistor device comprising:
Dependencies are inferred from the claim text.