Semiconductor device, array structure of semiconductor devices, neuromorphic circuit including the semiconductor devices, and computing apparatus including the neuromorphic circuit

A semiconductor device array structure comprising:

• a plurality of gate lines side by side in a first direction and each extending in a second direction;
• a plurality of semiconductor structures side by side in the second direction and crossing the plurality of gate lines, each of the plurality of semiconductor structures extending in the first direction;
• and
• a plurality of ferroelectric structures between the plurality of gate lines and the plurality of semiconductor structures,
• wherein each of the plurality of semiconductor structures comprises a semiconductor layer extending in the first direction and comprising a plurality of source regions and a plurality of drain regions which are apart from each other in the first direction, an insulating layer surrounding the semiconductor layer, and a first gate electrode layer surrounding the insulating layer,
• between a first drain region and a first source region which are adjacent to each other among the plurality of source regions and the plurality of drain regions, a ratio C2/C1 of a second capacitance C2 between the first gate electrode layer and one of the plurality of gate lines, which is adjacent to the first gate electrode layer, to a first capacitance C1 between the semiconductor layer and the first gate electrode layer is about 1/20 to about ⅕.

A neuromorphic circuit comprising:

• a pre-synaptic neuron circuit;
• a pre-synaptic line extending in a first direction from the pre-synaptic neuron circuit;
• a post-synaptic neuron circuit;
• a post-synaptic line extending from the post-synaptic neuron circuit in a second direction crossing the first direction;
• and
• a synaptic circuit at an intersection between the pre-synaptic line and the post-synaptic line,
• wherein the synaptic circuit comprises a semiconductor device comprising a semiconductor layer extending in the first direction and comprising a source region and a drain region, which are apart from each other in the first direction, an insulating layer surrounding the semiconductor layer, a first gate electrode layer surrounding the insulating layer, a ferroelectric layer on the first gate electrode layer, and a second gate electrode layer provided on the ferroelectric layer,
• wherein between the source region and the drain region, a ratio C2/C1 of a second capacitance C2 between the first gate electrode layer and the second gate electrode layer to a first capacitance C1 between the semiconductor layer and the first gate electrode layer is about 1/20 to about ⅕.