DMOS transistor having thick gate oxide and STI and method of fabricating

An integrated circuit (IC) chip having a double-diffused metal oxide silicon (DMOS) transistor, the transistor comprising:

• a source region having a first dopant type;
• an extended drain region coupled to a drain contact region, the extended drain region and the drain contact region having the first dopant type;
• a gate region having a second dopant type that is opposite the first dopant type;
• a shallow trench isolation (STI) structure overlying the extended drain region;
• a gate oxide layer overlying the gate region and a portion of the extended drain region;
• and
• a gate structure on the gate oxide layer, the gate structure having a gap, having a width of between 0.4 and 1.0 microns, overlying an intersection of an edge of the STI structure with the gate oxide layer, the gap filled with a dielectric.

An integrated circuit (IC), comprising:

• a source region having a first conductivity type located over a semiconductor layer having a second opposite conductivity type;
• a drain region and a drain contact region within the drain region, the drain region and the drain contact region located over the semiconductor layer and having the first conductivity type;
• a gate structure having a nonlinear bottom surface overlying the semiconductor layer and having a dielectric filled gap over the drain region;
• and
• a shallow trench isolation (STI) structure overlying the drain region and having an interface with the drain region that intersects a top surface of the semiconductor layer under the gap.

An integrated circuit (IC), comprising:

• a source region having a first conductivity type located over a semiconductor layer having a second opposite conductivity type;
• a drain region and a drain contact region within the drain region, the drain region and the drain contact region located over the semiconductor layer and having the first conductivity type;
• a gate structure overlying the semiconductor layer and having a dielectric filled gap, having a width of between 0.4 and 1.0 microns, over the drain region;
• and
• a shallow trench isolation (STI) structure overlying the drain region and having an interface with the drain region that intersects a top surface of the semiconductor layer under the gap.

A transistor, comprising:

• a source region and a drain region both having a first conductivity type and located over a semiconductor layer having a second opposite conductivity type;
• a gate structure having a nonlinear bottom surface that overlies the drain region and extends to the source region, the gate structure having a dielectric filled gap over the drain region;
• and
• a shallow trench isolation (STI) structure overlying the drain region and having an interface with the drain region that intersects a top surface of the semiconductor layer under the gap.

An integrated circuit (IC) chip having a double-diffused metal oxide silicon (DMOS) transistor, the transistor comprising:

• a source region having a first dopant type;
• an extended drain region coupled to a drain contact region, the extended drain region and the drain contact region having the first dopant type;
• a gate region having a second dopant type that is opposite the first dopant type;
• a shallow trench isolation (STI) structure overlying the extended drain region;
• a gate oxide layer overlying the gate region and a portion of the extended drain region;
• and
• a gate structure entirely on the gate oxide layer, the gate structure having a gap overlying an intersection of an edge of the STI structure with the gate oxide layer, the gap filled with a dielectric.

An integrated circuit (IC) chip having a double-diffused metal oxide silicon (DMOS) transistor, the transistor comprising:

• a source region having a first dopant type;
• an extended drain region coupled to a drain contact region, the extended drain region and the drain contact region having the first dopant type;
• a gate region having a second dopant type that is opposite the first dopant type;
• a shallow trench isolation (STI) structure overlying the extended drain region;
• a gate oxide layer overlying the gate region and a portion of the extended drain region;
• and
• a gate structure on the gate oxide layer, the gate structure having a gap overlying an intersection of an edge of the STI structure with the gate oxide layer, the gap filled with a dielectric, a surface of the gate oxide layer being nonlinear beneath the gap.

An integrated circuit (IC) chip having a double-diffused metal oxide silicon (DMOS) transistor, the transistor comprising:

• a source region having a first dopant type;
• an extended drain region coupled to a drain contact region, the extended drain region and the drain contact region having the first dopant type;
• a gate region having a second dopant type that is opposite the first dopant type;
• a shallow trench isolation (STI) structure overlying the extended drain region;
• a gate oxide layer overlying the gate region, a portion of the extended drain region and no portion of the source region;
• and
• a gate structure on the gate oxide layer, the gate structure having a gap overlying an intersection of an edge of the STI structure with the gate oxide layer, the gap filled with a dielectric.

An integrated circuit (IC), comprising:

• a source region having a first conductivity type located over a semiconductor layer having a second opposite conductivity type;
• a drain region and a drain contact region within the drain region, the drain region and the drain contact region located over the semiconductor layer and having the first conductivity type;
• a gate structure overlying the semiconductor layer and having a dielectric filled gap over the drain region;
• and
• a nonlinear shallow trench isolation (STI) structure overlying the drain region and having an interface with the drain region that intersects a top surface of the semiconductor layer under the gap.

A transistor, comprising:

• a source region and a drain region both having a first conductivity type and located over a semiconductor layer having a second opposite conductivity type;
• a gate structure that overlies the drain region and extends to the source region, the gate structure having a dielectric filled gap over the drain region;
• and
• a nonlinear shallow trench isolation (STI) structure overlying the drain region and having an interface with the drain region that intersects a top surface of the semiconductor layer under the gap.