Uniform implant regions in a semiconductor ridge of a FinfET
AssigneeTexas Instruments Incorporated
InventorMing-Yeh Chuang
Life of this patent
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Abstract
A method for fabricating an integrated circuit is disclosed. The method comprises forming a semiconductor ridge over a semiconductor surface of a substrate and forming an implant screen on a top and sidewalls of the semiconductor ridge. The implant screen is at least two times thicker on the top of the semiconductor ridge relative to the sidewalls of the semiconductor ridge. The method further comprises implanting a dopant into the top and sidewalls of the semiconductor ridge.
Claims20
An integrated circuit, comprising:
- a semiconductor fin located over a substrate, the fin having a top surface and side surfaces;
- and
- a doped region of the fin doped with phosphorous and arsenic, the top surface of the fin having a greater concentration of phosphorous than the side surfaces, and the side surfaces having a greater concentration of arsenic than the top surface.
An integrated circuit (IC), comprising:
- a semiconductor fin located over a substrate;
- and
- a conformal dielectric layer over the fin, including sidewall portions over side surfaces of the fin and a top portion over a top surface of the fin,
- wherein the sidewall portions of the dielectric layer have a first thickness and the top portion of the dielectric layer has a second thickness at least about two times the first thickness.
An integrated circuit, comprising:
- a transistor having drift region including a semiconductor fin, the fin having a top surface, side surfaces, and a doped region, the doped region including first and second dopants having a same conductivity type, the top surface of the fin having a greater concentration of the first dopant than the side surfaces, and the side surfaces having a greater concentration of the second dopant than the top surface.
An integrated circuit, comprising:
- a semiconductor fin located over a substrate, the fin having a top surface and side surfaces;
- and
- a doped region of the fin including first and second dopants having a same conductivity type, the top surface of the fin having a greater concentration of the first dopant than the side surfaces, and the side surfaces having a greater concentration of the second dopant than the top surface, wherein a net concentration of dopants having the same conductivity type varies by no more than ±50% between the top surface of the fin and the side surfaces of the fin.
An integrated circuit, comprising:
- a semiconductor fin located over a substrate, the fin having a top surface and side surfaces;
- and
- a doped region of the fin including first and second dopants having a same conductivity type, the top surface of the fin having a greater concentration of the first dopant than the side surfaces, and the side surfaces having a greater concentration of the second dopant than the top surface, wherein the top surface of the fin and the side surfaces of the fin have about a same total dopant concentration.
Dependencies are inferred from the claim text.