Field effect transistor, preparation method thereof and integrated circuit

A field effect transistor (FET), comprising:

• a substrate;
• a gate electrode, a gate dielectric layer, and a channel layer sequentially stacked on the substrate, wherein the channel layer is made of a two-dimensional (2D) material, and the gate electrode is closer to the substrate than the channel layer;
• an insulating layer, an etching stop layer, and a protective layer sequentially stacked on the channel layer, wherein the insulating layer is in direct contact with the channel layer and is electrically insulated, and the FET defines two through holes extending through the insulating layer, the etching stop layer, and the protective layer and exposing the channel layer;
• and
• a source electrode and a drain electrode respectively in a corresponding one of the two through holes and forming a top contact with the channel layer.

An integrated circuit, comprising a peripheral circuit and at least one FET electrically connected to the peripheral circuit, the at least one FET comprising:

• a substrate;
• a gate electrode, a gate dielectric layer, and a channel layer sequentially stacked on the substrate, wherein the channel layer is made of a two-dimensional (2D) material, and the gate electrode is closer to the substrate than the channel layer;
• an insulating layer, an etching stop layer, and a protective layer sequentially stacked on the channel layer, wherein the insulating layer is electrically insulated and in direct contact with the channel layer, and the FET defines two through holes extending through the insulating layer, the etching stop layer, and the protective layer and exposing the channel layer;
• and
• a source electrode and a drain electrode respectively in a corresponding one of the two through holes and forming a top contact with the channel layer.